Electrically alterable non-volatile memory with n-bits per cell

Abstract

An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of the memory cells are preferably arranged in a matrix of rows and columns disposed substantially in a rectangle, with a plurality of word lines coupled with memory gate electrodes intersecting a first side of the rectangle substantially perpendicularly, a plurality of bit lines coupled with memory drain-source current paths intersecting a second side of the rectangle substantially perpendicularly (the second side also substantially perpendicularly intersecting the first side), a row select circuit being disposed at the first side for coupling with the word lines, and peripheral circuitry including a column select circuit and a sense circuit being disposed at the second side.

1 . For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, electrons being capable of being injected into the floating gate, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: 
 setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to one state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, and    reading status of the one non-volatile multi-level memory cell from an output from a bit line coupled to a drain terminal of the one non-volatile multi-level memory cell,    wherein the operation of setting the parameter includes a program operation, in which electrons are injected into the floating gate of the one non-volatile multi-level memory cell using at least one programming voltage applied to the bit line,    wherein the program operation includes a series of programming operations each followed by a related verifying operation, and    wherein the series of programming operations includes a first programming operation and a second programming operation after the first programming operation, the duration of the second programming operation being shorter than that of the first programming operation.    
   
   
       2 - 75 . (canceled)