US2006224857A1PendingUtilityA1

Locking entries into translation lookaside buffers

Assignee: O'CONNOR DENNIS MPriority: Mar 29, 2005Filed: Mar 29, 2005Published: Oct 5, 2006
Est. expiryMar 29, 2025(expired)· nominal 20-yr term from priority
G06F 12/126G06F 12/1027
47
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional operations. A software managed lookaside buffer may be particularly involved in locking particular translations. As a result, the software's job is made simpler since it has a relatively simpler, software managed translation lookaside buffer to manage for locking translations.

Claims

exact text as granted — not AI-modified
1 . A method comprising: 
 providing two translation lookaside buffers for one microprocessor.    
   
   
       2 . The method of  claim 1  including providing a software and a hardware managed translation lookaside buffer for one microprocessor.  
   
   
       3 . The method of  claim 2  including providing a page table walk logic handled by said hardware managed translation lookaside buffer.  
   
   
       4 . The method of  claim 3  wherein, when a request for a translation from a linear to physical address is received, checking the software managed translation lookaside buffer to determine whether or not the translation is resident therein before checking said hardware managed translation lookaside buffer.  
   
   
       5 . The method of  claim 4  including checking said hardware managed translation lookaside buffer for said translation if said translation is not in said software managed translation lookaside buffer.  
   
   
       6 . The method of  claim 5  including, if said translation is not in said hardware managed translation lookaside buffer, obtaining the translation from a page table walk logic.  
   
   
       7 . The method of  claim 6  including returning the translation from the page table walk logic to said hardware managed translation lookaside buffer.  
   
   
       8 . The method of  claim 2  including locking translations in said software managed translation lookaside buffer.  
   
   
       9 . The method of  claim 2  including managing the software managed translation lookaside buffer in a restricted mode.  
   
   
       10 . An article storing instructions that, if executed, enable a processor-based system to: 
 search in a software managed translation lookaside buffer for a translation from a linear to a physical address and, if the translation is not resident in said software managed translation lookaside buffer, look for said translation in a hardware managed translation lookaside buffer.    
   
   
       11 . The article of  claim 10  further storing instructions that, if executed, enable a processor-based system to obtain translations from a table walk logic exclusively via a hardware managed translation lookaside buffer instead of said software managed translation lookaside buffer.  
   
   
       12 . The article of  claim 10  further storing instructions that, if executed, enable a processor-based system to lock translations in said software managed translation lookaside buffer.  
   
   
       13 . The article of  claim 10  further storing instructions that, if executed, enable a processor-based system to manage the software managed translation lookaside buffer in a restricted mode.  
   
   
       14 . The article of  claim 10  further storing instructions that, if executed, enable a processor-based system to return a translation from a page table walk logic to said hardware managed translation lookaside buffer.  
   
   
       15 . A system comprising: 
 a processor comprising a pair of translation lookaside buffers, only one of said buffers having page table walk logic; and    a wireless interface coupled to said processor.    
   
   
       16 . The system of  claim 15  wherein said wireless interface includes a dipole antenna.  
   
   
       17 . The system of  claim 15  wherein one of said buffers is a software managed translation lookaside buffer and the other one is a hardware managed translation lookaside buffer that is coupled to a page table walk logic.  
   
   
       18 . The system of  claim 17  wherein said software managed translation lookaside buffer is consulted first and only if a translation is not in said software managed translation lookaside buffer is said hardware managed translation lookaside buffer checked for the translation.  
   
   
       19 . The system of  claim 18  including a page table walk logic coupled exclusively to said hardware managed translation lookaside buffer.  
   
   
       20 . The system of  claim 19  wherein the software managed translation lookaside buffer to determine whether or not the translation is resident therein before said hardware managed translation lookaside buffer is checked for said translation.  
   
   
       21 . The system of  claim 20  wherein said page table walk logic to return a translation from the page table walk logic to said hardware managed translation lookaside buffer.  
   
   
       22 . The system of  claim 17 , said processor to lock translations exclusively in said software managed translation lookaside buffer.  
   
   
       23 . The system of  claim 17  wherein said software managed translation lookaside buffer is managed in a restricted mode.

Join the waitlist — get patent alerts

Track US2006224857A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.