Semiconductor integrated circuit

Abstract

In a dynamic reconfigurable processor, a mechanism for effectively storing configuration data with a small hardware scale and improving processing performance is provided. Also, a sequence mechanism that is easy to be implemented with flexibility and a high operating frequency being both achieved is provided. The configuration data is hierarchically stored, and without suspending a process in a processing unit, configuration data required for subsequent processing is transferred in advance from a first storage area to a second storage area. Also, with a plurality of sequence modes, a condition determination process is performed on different sequence conditions.

1 . A semiconductor integrated circuit comprising: 
 a processing unit including a plurality of processing cells for performing a process;    a data memory for retaining a process data;    a data memory control unit including a plurality of data memory control cells for controlling an access to the data memory;    a sequence manager for controlling a state sequence;    a configuration manager for controlling a transfer of configuration data defining logical functions of the processing cells and the data memory control cells;    a first bus for transmitting the configuration data to the configuration manager; and    a second bus for connecting the configuration manager, and the data memory control unit and the processing unit, wherein    the configuration manager includes a first storage area for storing the configuration data transferred via the first bus,    each of the plurality of processing cells and the plurality of data memory control cells includes a second storage area for storing the configuration data transferred via the second bus from the configuration manager, and    each of the plurality of processing cells and the plurality of data memory control cells can dynamically reconfigure the logic functions by changing the configuration data.    
   
   
       2 . The semiconductor integrated circuit according to  claim 1 , wherein 
 the first storage area has a plurality of banks capable of storing a plurality of pieces of configuration data.    
   
   
       3 . The semiconductor integrated circuit according to  claim 2 , wherein 
 Each of the plurality of banks is independently capable of writing and reading.    
   
   
       4 . The semiconductor integrated circuit according to  claim 1 , wherein 
 an amount of data transfer in the second bus by unit time is larger than an amount of data transfer in the first bus.    
   
   
       5 . The semiconductor integrated circuit according to  claim 1 , wherein 
 the sequence manager includes a sequence control register capable of setting a plurality of sequence modes, and a sequence control unit for determining whether a sequence condition is satisfied, and    the sequence control unit performs a sequence condition determination operation based on each different sequence condition in accordance with a sequence mode set in the sequence control register.    
   
   
       6 . The semiconductor integrated circuit according to  claim 5 , wherein 
 the sequence manager includes a plurality of sequence control tables each having stored therein a different sequence condition for each sequence mode, and performs the sequence condition determination operation and a sequence operation in accordance with a sequence control table corresponding to each sequence mode.    
   
   
       7 . The semiconductor integrated circuit according to  claim 1 , wherein 
 the sequence manager includes a sequence control table with fields allowing a plurality of sequence conditions and a state after transition to be stored therein, and a sequence control unit for determining whether the sequence conditions are satisfied, and    the sequence control unit determines whether the sequence conditions are satisfied in accordance with setting contents of thee sequence control table, and performs a sequence operation.    
   
   
       8 . The semiconductor integrated circuit according to  claim 7 , wherein 
 the sequence manager includes a plurality of sequence control tables having stored therein a different sequence condition for each sequence mode, and performs a sequence condition determination operation and a sequence operation in accordance with a sequence control table corresponding to each sequence mode.    
   
   
       9 . The semiconductor integrated circuit according to  claim 1 , wherein 
 the sequence manager generates a preload request for the configuration data when a predetermined sequence condition is satisfied, and    the configuration manager has a function of transferring the configuration information from the first storage area to the second storage area upon the preload request from the sequence manager.    
   
   
       10 . The semiconductor integrated circuit according to  claim 1 , wherein 
 the second storage area includes a plurality of banks capable of storing a plurality of pieces of configuration data, and is configured so as to be able to store, during a process based on the configuration data stored in a first bank, the configuration data supplied from the configuration manager in a second bank that is different from the first bank.    
   
   
       11 . The semiconductor integrated circuit according to  claim 10 , wherein 
 the configuration manager has a function of specifying, from among the plurality of banks capable of storing a plurality of pieces of configuration data, non-active banks not corresponding to an active process, and transferring the configuration data to one of the non-active banks.    
   
   
       12 . The semiconductor integrated circuit according to  claim 10 , wherein 
 the configuration manager has a storage area indicating a correspondence between identifiers for identifying a plurality of states, and the plurality of banks.    
   
   
       13 . The semiconductor integrated circuit according to  claim 10 , wherein 
 the configuration manager has a storage area for storing a relation between identifiers for identifying a plurality of states, and addresses of a transfer destination and a transfer source of the configuration data in order to transfer the plurality of pieces of configuration data from the first storage area to the second storage area.    
   
   
       14 . A semiconductor integrated circuit comprising: 
 a processing unit including a plurality of processing cells for performing a process;    a data memory for retaining a process data;    a data memory control unit including a plurality of data memory control cells for controlling an access to the data memory;    a sequence manager for controlling a state sequence; and    a configuration manager for controlling a transfer of configuration data defining logical functions of the processing cells and the data memory control cells, wherein    the processing cells and the data memory control cells can dynamically reconfigure the logical functions by changing the configuration data,    the sequence manager has a first table having stored therein a number provided to a switch destination and a second table having stored therein the number provided to the switch destination, a current number, and a switching condition, and    the sequence manager has a function of switching, during operation, between a first mode of using the first table and a second mode of using the second table.    
   
   
       15 . The semiconductor integrated circuit according to  claim 14 , wherein 
 the configuration manager includes a first storage area having stored in the configuration information transferred from an external memory via a first bus, and    each of the plurality of processing cells and the plurality of data memory control cells includes a second storage area for storing the configuration data transferred via a second bus from the configuration manager.