Vertical group III-nitride light emitting device and method for manufacturing the same

Abstract

A vertical group III-nitride light emitting device and a manufacturing method thereof are provided. The light emitting device comprises: a conductive substrate; a p-type clad layer stacked on the conductive substrate; an active layer stacked on the p-type clad layer; an n-doped Al x Ga y In 1-x-y N layer stacked on the active layer; an undoped GaN layer stacked on the n-doped layer; and an n-electrode formed on the undoped GaN layer. The undoped GaN layer has a rough pattern formed on a top surface thereof.

1 . A vertical group III-nitride light emitting device comprising: 
 a conductive substrate;    a p-type clad layer stacked on the conductive substrate;    an active layer stacked on the p-type clad layer;    an n-doped layer stacked on the active layer, the n-doped layer having a composition expressed by Al x Ga y In 1-x-y N, where 0≦x≦1, 0≦y≦1 and 0≦x+y≦1;    an undoped GaN layer stacked on the n-doped layer; and    an n-electrode formed on the undoped GaN layer,    wherein the undoped GaN layer has a rough pattern formed on a top surface thereof.    
   
   
       2 . The vertical group III-nitride light emitting device according to  claim 1 , wherein the undoped GaN layer does not have a rough pattern on an area where the n-electrode is formed.  
   
   
       3 . The vertical group III-nitride light emitting device according to  claim 1 , further comprising a reflective layer formed between the conductive substrate and the p-type clad layer.  
   
   
       4 . The vertical group III-nitride light emitting device according to  claim 3 , wherein the reflective layer comprises one selected from a group consisting of a CuInO 2 /Ag layer, a CuInO 2 /Al layer and an Ni/Ag/Pt layer.  
   
   
       5 . The vertical group III-nitride light emitting device according to  claim 1 , further comprising a transparent electrode layer formed on the undoped GaN layer.  
   
   
       6 . The vertical group III-nitride light emitting device according to  claim 1 , further comprising a conductive adhesive layer formed between the conductive substrate and the p-type clad layer.  
   
   
       7 . The vertical group III-nitride light emitting device according to  claim 6 , wherein the conductive adhesive layer comprises one selected from a group consisting of Au, Au—Sn, Sn, In, Au—Ag and Pb—Sn.  
   
   
       8 . The vertical group III-nitride light emitting device according to  claim 6 , further comprising a reflective layer formed between the conductive adhesive layer and the p-type clad layer.  
   
   
       9 . The vertical group III-nitride light emitting device according to  claim 1 , wherein the conductive substrate comprises a metal substrate or a silicon substrate.  
   
   
       10 . The vertical group III-nitride light emitting device according to  claim 9 , wherein the metal substrate comprises one selected from a group consisting of W, Cu, Ni, Ti and alloys of at least two thereof.  
   
   
       11 . The vertical group III-nitride light emitting device according to  claim 1 , wherein the rough pattern comprises convexes or concaves which are spaced from each other in the range of 20 nm to 100 μm, and each have a width and a height of 20 nm to 100 μm, respectively.  
   
   
       12 . The vertical group III-nitride light emitting device according to  claim 1 , wherein the rough pattern comprises convexes or concaves which are spaced from each other in the range of 200 nm to 3 μm, and each have a width and a height of 200 nm to 3 μm, respectively.  
   
   
       13 . The vertical group III-nitride light emitting device according to  claim 1 , wherein the rough pattern comprises a photonic crystal.  
   
   
       14 . The vertical group III-nitride light emitting device according to  claim 1 , wherein the rough pattern has one sectional shape selected from a group consisting of hemisphere, rectangle and serration.  
   
   
       15 . A method for manufacturing a vertical group III-nitride light emitting device comprising steps of: 
 (i) preparing a basic substrate having a rough pattern formed on a top surface thereof;    (ii) forming an n-type clad layer, an active layer and a p-type clad layer sequentially on the basic substrate, the clad layers and the active layer having compositions expressed by Al x Ga y In 1-x-y N, where 0≦x≦1, 0≦y≦1, and 0≦x+y≦1;    (iii) forming a conductive substrate on the p-type clad layer;    (iv) removing the basic substrate so as to expose a rough pattern formed on a bottom surface of the n-type clad layer; and    (v) forming an n-electrode on a partial area of the exposed bottom surface of the n-type clad layer.    
   
   
       16 . The method according to  claim 15 , wherein the basic substrate comprises one selected from a group consisting of sapphire, SiC, GaN and AIN.  
   
   
       17 . The method according to  claim 15 , wherein in the step (i), the rough pattern is not formed on a top surface area of the basic substrate corresponding to the n-electrode.  
   
   
       18 . The method according to  claim 15 , wherein the step (ii) comprises: 
 forming an undoped GaN layer on the basic substrate; and    forming an n-doped layer on the undoped GaN layer, the n-doped layer having a composition expressed by Al x Ga y In 1-x-y N, where 0≦x≦1, 0≦y≦1 and 0≦x+y≦1.    
   
   
       19 . The method according to  claim 15 , wherein the step (iii) comprises bonding the conductive substrate to the p-clad layer via a conductive adhesive layer.  
   
   
       20 . The method according to  claim 15 , wherein the step (iii) comprises forming the conductive substrate on the p-type clad layer via plating, deposition or sputtering.  
   
   
       21 . The method according to  claim 15 , further comprising forming a reflective layer on the p-type clad layer between the step (ii) and the step (iii).  
   
   
       22 . The method according to  claim 21 , wherein the reflective layer comprises one selected from a group consisting of a CuInO 2 /Ag layer, a CuInO 2 /Al layer and an Ni/Ag/Pt layer.  
   
   
       23 . The method according to  claim 15 , further comprising forming a transparent electrode layer on the n-type clad layer after the step (iv).  
   
   
       24 . The method according to  claim 15 , wherein the rough pattern formed on the basic substrate comprises convexes or concaves which are spaced from each other in the range of 20 nm to 100 μm, and each have a width and a height of 20 nm to 100 μm, respectively.  
   
   
       25 . The method according to  claim 15 , wherein the rough pattern formed on the basic substrate comprises convexes or concaves which are spaced from each other in the range of 200 nm to 3 μm, and each have a width and a height of 200 nm to 3 μm, respectively.  
   
   
       26 . The method according to  claim 15 , wherein the step (i) is conducted such that the rough pattern has a sectional shape of hemisphere, rectangle or serration.