GaN-based high electron mobility transistor and method for making the same

Abstract

A high electron mobility transistor including: a GaN material system based heterostructure; a passivating nitride layer over the heterostructure and defining a plurality of openings; and a plurality of electrical contacts for the heterostructure and formed through the openings.

1 - 6 . (canceled)  
   
   
       7 . A high electron mobility transistor comprising: 
 a GaN material system based heterostructure;    a passivating nitride layer over said heterostructure and defining a plurality of openings;    a plurality of electrical contacts for said heterostructure and being formed through said openings; and    a gate contact being formed through one of said openings and in contact with the GaN material system based heterostructure, wherein a portion of said passivating nitride layer is under a portion of the gate contact.    
   
   
       8 . The transistor of  claim 7 , wherein said electrical contacts comprise source and drain contacts comprising one of: Ti—Al—Ti—Au, Ti—Al—Mo—Au, Ti—Al—Ni—Au, or Ti—Al—Pt—Au, and a gate contact comprising one of: Ni/Pt/Au, Ni/Au, Pt/Au, or Ir/Au.  
   
   
       9 . The transistor of  claim 7 , wherein said passivating nitride layer has a thickness between about 450 and 2000 angstroms.  
   
   
       10 - 15 . (canceled)  
   
   
       16 . A high electron mobility transistor comprising: 
 a mesa structure having a plateau and formed by a method comprising: 
 providing a dielectric film over a GaN material system based heterostructure;  
 providing a photo resist mask over said dielectric film;  
 etching said dielectric film and heterostructure dependently upon said photo resist mask into a mesa structure; and  
 removing said photo resist mask and remaining portions of said dielectric film;  
   a passivating nitride layer over said plateau and defining at least one opening; and    a gate contact extending through said opening and in contact with the GaN material system based heterostructure, wherein a portion of said passivating nitride layer is under at least one portion of said gate contact.    
   
   
       17 . The transistor of  claim 16 , wherein said etching comprises reactive ion etching said dielectric film and inductive coupled plasma etching said heterostructure.  
   
   
       18 . (canceled)  
   
   
       19 . The transistor of  claim 16 , wherein said GaN material system based heterostructure comprises an AlGaN/GaN double heterostructure.  
   
   
       20 - 21 . (canceled)  
   
   
       22 . A high electron mobility transistor comprising: 
 a GaN material system based heterostructure;    doped source and drain contact regions for the GaN material system based heterostructure, wherein said doped source and drain contact regions are doped with at least one of Si+, Ge+, Si+ and N+, or Ge+ and N+;    a passivating layer over said GaN material system based heterostructure; and    a gate contact region in contact with the GaN material system based heterostructure, wherein a portion of said passivating nitride layer is under at least one portion of said gate contact.    
   
   
       23 . The transistor of  claim 22 , further comprising thermally activating said dopant in said heterostructure.  
   
   
       24 . The transistor of  claim 22 , further comprising forming contact electrodes over said dopant in said heterostructure.  
   
   
       25 . The transistor of  claim 22 , wherein said GaN material system based heterostructure comprises at least one AlGaN/GaN heterostructure.  
   
   
       26 . The transistor of  claim 22 , wherein said GaN material system based heterostructure comprises a dense nitride passivation layer.  
   
   
       27 . The transistor of  claim 22 , wherein said GaN material system based heterostructure comprises a doped channel.  
   
   
       28 . The transistor of  claim 22 , wherein said GaN material system based heterostructure comprises at least one AlGaN/GaN heterostructure further comprising an AlN layer.  
   
   
       29 . The transistor of  claim 22 , wherein said GaN material system based heterostructure comprises a double AlGaN/GaN heterostructure.  
   
   
       30 . The transistor of  claim 22 , wherein said GaN material system based heterostructure comprises a mesa region having gate, drain and source electrodes formed thereon.  
   
   
       31 . The transistor of  claim 22 , further comprising a mesa structure having a plateau, wherein said passivating layer is over said plateau.  
   
   
       32 . A high electron mobility transistor comprising: 
 a GaN material system based heterostructure;    doped source and drain contact regions for the GaN material system based heterostructure, wherein said doped source and drain contact regions are doped with at least one of Si+, Ge+, Si+ and N+, or Ge+ and N+;    a passivating layer over said GaN material system based heterostructure;    a channel laterally extending between the source and drain contact regions; and,    a gate electrode having a portion extending through the passivating layer, the gate electrode having an overall width less than the width of the laterally extending channel.    
   
   
       33 . The transistor of  claim 32 , further comprising a mesa structure having a plateau, wherein said passivating layer is over said plateau.