Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same

Abstract

Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

1 . A method for manufacturing a thin film transistor array panel for a liquid crystal display, comprising the steps of: 
 forming a gate wire on an insulating substrate by a first photolithography process;    forming a quadruple layer including a gate insulating layer, a semiconductor layer, an ohmic contact layer and a data conductor layer on the substrate and the gate wire by a second photolithography process;    forming a conductive pattern on the data conductor layer by a third photolithography process;    etching the portion of the data conductor layer not covered by the conductive pattern to form a data wire;    etching the ohmic contact layer not covered by the data wire; and    forming a passivation layer pattern on the conductive pattern by a fourth photolithography process.    
   
   
       2 .- 21 . (canceled)  
   
   
       22 . A thin film transistor array panel for a liquid crystal display comprising: 
 a gate wire formed on an insulating substrate and including a plurality of gate lines extending to a first direction, gate electrodes connected to the gate line, and gate pads connected to an end of the gate line;    a gate insulating layer having contact holes exposing the gate pad and formed in a matrix shape on the gate wire and the substrate;    a semiconductor layer formed on the gate insulating layer;    a data wire formed on the semiconductor layer and including a plurality of data lines extending to a second direction crossing the gate line, source electrodes adjacent to the gate electrode, drain electrode separated from the data line and the source electrode and located at the opposite side of the source electrode with respect to the gate electrode, and data pads connected to an end of the data line;    a conductive pattern including a plurality of first patterns formed on the source electrode and the data line, second patterns formed on the drain electrode, third patterns formed on the data pad, and pixel electrodes connected to the second pattern; and    a passivation layer formed on the conductive pattern, the semiconductor pattern and the substrate, and having a plurality of first openings exposing the pixel electrode, second openings exposing the gate insulating layer between the two adjacent data lines, third openings located on the gate pad, and fourth openings exposing the third pattern,    wherein the data wire is only formed between the conductive pattern and the semiconductor layer, the semiconductor layer is formed on the whole gate insulating layer except for the portion under the second opening, and the portions of the semiconductor layer under the two adjacent data lines are separated from each other.    
   
   
       23 .- 30 . (canceled)  
   
   
       31 . A method for manufacturing a thin film transistor array panel, comprising the steps of: 
 forming a gate wire including a plurality of gate lines and gate pads by a first photolithography process;    depositing a first insulating layer, a semiconductor layer, an ohmic contact layer and a metal layer on the gate wire;    forming a metal layer pattern, an ohmic contact layer pattern, a semiconductor layer pattern and a first insulating layer pattern that have a matrix shape layout overlapping the gate wire except for the gate pad by a second photolithography process;    depositing a transparent conductor layer;    forming a transparent conductor pattern including a pixel electrode, a plurality of redundant date lines, redundant source electrodes, redundant drain electrodes, redundant data pad and redundant gate pad by a third photolithography process;    etching out the portion of the metal layer not covered by the transparent conductor pattern and the ohmic contact layer thereunder;    depositing a second insulating layer;    forming a passivation layer pattern having openings respectively exposing the gate pad, the data pad, the pixel electrode and the portion of the semiconductor layer connecting the adjacent data line; and    etching out the portion of the semiconductor layer exposed through the openings.    
   
   
       32 .- 53 . (canceled)