Method and system for embedded disk controllers

Abstract

An embedded disk controller comprises a main processor in communication with a first bus. A second processor is in communication with a second bus. An external bus controller (EBC) is in communication with the first bus and in communication with external devices via an external bus interface. A history module is located in the embedded disk controller, communicates with the first bus and the second bus, and at least one of monitors transaction information of one of said external devices and masks information of one of said external devices via the EBC based on setup information, wherein the EBC and the history module are located on at least on of an integrated circuit (IC) and a system on a chip (SOC) with the embedded disk controller.

1 . An embedded disk controller, comprising: 
 a main processor in communication with a first bus;    a second processor in communication with a second bus;    an external bus controller (EBC) in communication with the first bus and in communication with external devices via an external bus interface; and    a history module that is located in the embedded disk controller, that communicates with the first bus and the second bus, and that at least one of monitors transaction information of one of said external devices and masks information of one of said external devices via the EBC based on setup information,    wherein the EBC and the history module are located on at least one of an integrated circuit (IC) and a system on a chip (SOC) with the embedded disk controller.    
   
   
       2 . The embedded disk controller of  claim 1  further comprising an interrupt controller module that generates a fast interrupt to the main processor based on a fast interrupt request (FIQ).  
   
   
       3 . The embedded disk controller of  claim 1  wherein the EBC includes at least one of a segment descriptor register and a device range register, wherein the embedded disk controller programs timing characteristics of the external devices via the segment descriptor register and the main processor accesses address space of the external devices via the device range register.  
   
   
       4 . The embedded disk controller of  claim 1  wherein the history module records transaction information on at least one of the first bus and the second bus based on a register map.  
   
   
       5 . The embedded disk controller of  claim 4  wherein the register map stores a break point condition value that is set by the first processor and the history module stops recording the transaction information based on the break point condition value.  
   
   
       6 . The embedded disk controller of  claim 5  wherein the history module stores a trigger mode field value, wherein the history module records a predetermined number of entries after the break point condition value reaches a threshold based on the trigger mode field value.  
   
   
       7 . The embedded disk controller of  claim 1  wherein the history module at least one of: 
 stores a read mask field value and stops reading operations based on the read mask field value; and    stores a write mask field value and stops write operations based on the write mask field value.    
   
   
       8 . The embedded disk controller of  claim 1  wherein the history module stores an enable clock slam field value and the history module generates a signal that stops clocks in the embedded disk controller based on the enable clock slam field value.  
   
   
       9 . The embedded disk controller of  claim 1  further comprising a servo controller that communicates with the second processor via a servo controller interface and provides real time servo controller information to the second processor.  
   
   
       10 . The embedded disk controller of  claim 1  wherein the second processor is a digital signal processor (DSP) that communicates with the first main processor via an interface.  
   
   
       11 . The embedded disk controller of  claim 2  wherein the interrupt controller module generates a regular interrupt based on a regular interrupt request (IRQ).  
   
   
       12 . The embedded disk controller of  claim 11  wherein the interrupt controller module includes an interrupt generation module that generates a fast interrupt when an FIQ is pending and processes an IRQ based on priority when an FIQ is not pending.