System and method for a high-speed access architecture for semiconductor memory

Abstract

A memory device is provided, which includes a first device, a second device, and a memory cell. The first device is electrically connected to a first plurality of wires. The first device is adapted to generate a small swing signal in the first plurality of wires. The second device is electrically connected to the first device by the first plurality of wires. The memory cell is electrically connected to the second device by a second plurality of wires. The second device is adapted to sense a small swing signal in the first plurality of wires, and to generate a full swing signal on the second set of wires in response to the small swing signal. The memory cell stores the full swing signal.

1 . A method for operating memory devices, the method comprising: 
 generating a first small swing signal;    transmitting the first small swing signal through a first plurality of wires;    amplifying the first small swing signal to generate a full swing signal; and    storing a state corresponding to the full swing signal into a memory cell.    
   
   
       2 . The method of  claim 1  further comprising: 
 reading from the memory cell to generate a second small swing signal;    generating a third small swing signal from the second small swing signal; and    transmitting the third small swing signal through a second plurality of wires.    
   
   
       3 . The method of  claim 2 , wherein the first and the second plurality of wires are a same set of bi-directional wires, and wherein the steps of transmitting the first small swing signal and transmitting the third small swing signal are performed during different time frames.  
   
   
       4 . The method of  claim 2  further comprising enabling wordlines of the memory cell to reach a voltage equal to a magnitude of the full swing signal during the step of reading from the memory cell.  
   
   
       5 . The method of  claim 1  further comprising enabling enabling wordlines of the memory cell to reach a voltage equal to a magnitude of the full swing signal during the step of storing the state into the memory cell.  
   
   
       6 . The method of  claim 1 , wherein the first small swing signal has a magnitude less than about 50 percent a magnitude of the full swing signal.  
   
   
       7 . The method of  claim 6 , wherein the magnitude of the first small swing signal is equal to about 25 percent of the magnitude of the full swing signal.  
   
   
       8 . The method of  claim 1 , wherein the first plurality of wires comprises two wires or four wires.  
   
   
       9 . A method for operating memory devices, the method comprising: 
 reading from a memory cell to generate a first small swing signal;    generating a second small swing signal from the first small swing signal; and    transmitting the second small swing signal through a plurality of wires.    
   
   
       10 . The method of  claim 9  further comprising amplifying the second small swing signal.  
   
   
       11 . The method of  claim 9  further comprising enabling wordlines of the memory cell to reach a voltage equal to a magnitude of the full swing signal during the step of reading the memory cell.  
   
   
       12 . The method of  claim 9 , wherein the first and the second small swing signals have magnitudes less than about 50 percent a magnitude of the full swing signal.  
   
   
       13 . The method of  claim 9 , wherein the magnitudes of the first and the second small swing signals are each equal to about 25 percent of the magnitude of the full swing signal.  
   
   
       14 . The method of  claim 9 , wherein the plurality of wires comprises bi-directional wires, and wherein the plurality of wires is also used for transmitting signals for write operations of the memory cell.  
   
   
       15 . The method of  claim 9 , wherein the plurality of wires comprises two wires or four wires.  
   
   
       16 . A method for operating a memory device, the method comprising: 
 providing a memory cell;    connecting transmission buffers to the memory cell, wherein the transmission buffers are configured to interface with the memory cell; and    transmitting small swing signals between the transmission buffers and devices, wherein the small swing signals have magnitudes substantially smaller than a magnitude of a voltage supply of the memory device.    
   
   
       17 . The method of  claim 16 , wherein the transmission buffers comprise a write buffer for write operations and a read buffer for read operations.  
   
   
       18 . The method of  claim 16 , wherein the devices comprise a write driver for generating the small swing signals during write operations and a read amplifier for amplifying small swing signals during read operations.  
   
   
       19 . The method of  claim 16 , wherein, during write operations, the small swing signals are amplified to full swing signals before writing into the memory cell.  
   
   
       20 . The method of  claim 16 , wherein the small swing signals each have amplitudes of less than about 50 percent of the voltage supply.