Interconnects including members integral with bit lines, as well as metal nitride and metal silicide, and methods for fabricating interconnects and semiconductor device structures including the interconnects

Abstract

An interconnect includes a member that is integral and lacks a discernable boundary with a bit line, as well as metal nitride and metal silicide between the member and an active-device region of a semiconductor substrate. The interconnect may extend adjacent to and be insulated from a stacked capacitor structure to facilitate electrical communication between the active-device region and the bit line. Methods for fabricating such an interconnect are disclosed, as methods for fabricating semiconductor device structures that include one or more such interconnects.

1 . An interconnect for connecting an active-device region of a semiconductor substrate to a bit line extending above a semiconductor device structure, comprising: 
 metal silicide in contact with the active-device region;    a member in communication with the bit line, the member and the bit line comprising a unitary structure with no discernable boundary therebetween; and    metal nitride substantially confined between the metal silicide and the member.    
   
   
       2 . The interconnect of  claim 1 , wherein the metal nitride comprises titanium nitride.  
   
   
       3 . The interconnect of  claim 1 , wherein the metal nitride and the member comprise a buried metal diffusion structure.  
   
   
       4 . The interconnect of  claim 1 , wherein the metal silicide comprises at least one of titanium silicide and tungsten silicide.  
   
   
       5 . The interconnect of  claim 1 , wherein the member has a resistivity of less than about 5 μΩ-cm.  
   
   
       6 . The interconnect of  claim 1 , wherein the member comprises aluminum.  
   
   
       7 . An interconnect for connecting an active-device region of a semiconductor substrate to a bit line extending above a semiconductor device structure, comprising: 
 a member extending from the bit line, the member and the bit line comprising a unitary structure with no discernable boundary therebetween;    a metal silicide adjacent to the active-device region; and    metal nitride positioned between the metal silicide and the member, an entirety of the metal nitride being superimposed relative to the metal silicide.    
   
   
       8 . The interconnect of  claim 7 , wherein the metal silicide contacts the active-device region.  
   
   
       9 . The interconnect of  claim 7 , wherein the metal silicide contacts the member.  
   
   
       10 . The interconnect of  claim 7 , wherein the metal nitride comprises titanium nitride.  
   
   
       11 . The interconnect of  claim 7 , wherein adjacent portion of the metal silicide and the member comprise a buried metal diffusion structure.  
   
   
       12 . The interconnect of  claim 7 , wherein the metal silicide comprises at least one of titanium silicide and tungsten silicide.  
   
   
       13 . The interconnect of  claim 7 , wherein the member has a resistivity of less than about 5 μΩ-cm.  
   
   
       14 . The interconnect of  claim 7 , wherein the member comprises aluminum.  
   
   
       15 . A method for fabricating a semiconductor device structure, comprising: 
 forming at least one trench through at least one stacked capacitor structure to expose at least one active device region;    forming a buried metal diffusion layer within the trench;    forming metal nitride adjacent to the buried metal diffusion layer;    concurrently introducing conductive material over the at least one stacked capacitor structure and within the at least one trench, the metal nitride substantially confined between the buried metal diffusion layer and the conductive material; and    forming at least one bit line from conductive material located over at least the at least one stacked capacitor structure, with no discernable boundary between the at least one bit line and at least one member formed by conductive material within the at least one trench.    
   
   
       16 . The method of  claim 15 , further comprising: 
 electrically isolating the at least one trench from the at least one stacked capacitor structure.    
   
   
       17 . The method of  claim 15 , wherein forming the buried metal diffusion layer comprises forming a metal silicide layer on the surface of the at least one active-device region.  
   
   
       18 . The method of  claim 17 , wherein forming the buried metal diffusion layer includes selectively depositing the metal silicide layer.  
   
   
       19 . The method of  claim 17 , wherein forming the buried metal diffusion layer includes depositing a metal or metal nitride and annealing the metal or metal nitride layer to the at least one active-device region.  
   
   
       20 . The method of  claim 15 , wherein forming metal nitride comprises depositing metal nitride on the buried metal diffusion layer.  
   
   
       21 . The method of  claim 20 , wherein depositing metal nitride comprises selectively depositing metal nitride.  
   
   
       22 . The method of  claim 21 , further comprising: 
 selectively removing metal nitride from surfaces of the at least one trench and over the at least one stacked capacitor structure.    
   
   
       23 . The method of  claim 15 , wherein concurrently introducing comprises concurrently introducing conductive material comprising aluminum.  
   
   
       24 . The method of  claim 15 , wherein forming the at least one bit line comprises patterning the conductive material located over at least the at least one stacked capacitor structure.  
   
   
       25 . The method of  claim 15 , wherein forming the bit line comprising selectively removing the material from locations over the at least one stacked capacitor structure.  
   
   
       26 . The method of  claim 25 , wherein selectively removing includes planarizing the conductive material.  
   
   
       27 . The method of  claim 25 , wherein selectively removing includes etching the conductive material.