Trench isolation for semiconductor devices

Abstract

A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in regions directly below the isolation trench after partially filling the trench with the dielectric material. The dielectric along the sidewalls of the trenches can serve as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. The dielectric along the sidewalls of the trenches serves as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. After the ions are implanted in the substrate below the trenches, the remainder of the trench can be filled with the same or another dielectric material. The trench isolation technique can be used to fabricate memory, logic and imager devices which can exhibit reduced current leakage and/or reduced optical cross-talk.

1 - 67 . (canceled)  
   
   
       68 . An imaging device comprising: 
 a semiconductor substrate including a plurality of doped active pixel regions, said semiconductor substrate having a first doping concentration;    a field isolation region separating at least two of said active pixel regions, wherein said active pixel regions contain a photosensitive element, wherein said field isolation region includes an isolation trench, said isolation trench further including a first area filled with a first dielectric material forming at least sidewalls of said isolation trench, said sidewalls having a thickness, and a second area filled with a second dielectric material situated within said sidewalls, said first dielectric material being different than said second dielectric material; and    an ion implanted region provided below said second area having an increased doping concentration due to additional dopants in an area of said substrate between said separated active pixel regions, said increased doping concentration being higher than said first doping concentration of said substrate, wherein substantially all ions from said ion implanted region which increase said doping concentration are displaced away from said active pixel regions by a distance at least equal to a said sidewall thickness of said first area filled with said first dielectric material, and wherein said sidewall thickness of said first area is less than about forty percent the width of the isolation region and said sidewalls are arranged and configured to mask the substrate from said additional dopants.    
   
   
       69 . The imaging device of  claim 68 , wherein the first dielectric material has a thickness of at least about one hundred angstroms.  
   
   
       70 . The imaging device of  claim 68 , wherein the implanted ions establish a field threshold voltage.  
   
   
       71 . The imaging device of  claim 68 , wherein the ions are implanted into the substrate to a depth in a range of about 10 to 100 percent the depth of said first area filled with said first dielectric material.  
   
   
       72 . The imaging device of  claim 68 , wherein the ions are implanted into the substrate to a depth in a range of about 20 to 80 percent the depth of said first area filled with said first dielectric material.  
   
   
       73 . The imaging device of  claim 68 , wherein said first area also includes said first dielectric material provided on a bottom of said isolation trench and said second dielectric material provided over said first dielectric material provided at said bottom.  
   
   
       74 . The imaging device of  claim 68 , wherein said thickness of said sidewalls is sufficient to block said additional dopants from becoming implanted in the substrate near said active pixel regions, the doped region having an implanted ion profile in which implanted ions are displaced from an alignment with said active pixel regions by masking due to said sidewall thickness.  
   
   
       75 . The imaging device of  claim 68 , wherein the ion implanted region includes respective shallow and deep implants.  
   
   
       76 . The imaging device of  claim 75 , wherein the shallow implants establish a field threshold voltage, and wherein the deep implants are implanted into the substrate to a depth in a range of about 10 to 100 percent the depth of said first area filled with said first dielectric material.  
   
   
       77 . The imaging device of  claim 75 , wherein the implanted ions have a conductivity type that is the same as the substrate.  
   
   
       78 . The imaging device of  claim 68 , wherein the imaging device is a CMOS imager or a CCD imager.  
   
   
       79 . An imaging device comprising: 
 a semiconductor substrate including a first region of a predefined conductivity type;    a field isolation region for separating said first region into at least two active pixel regions, each of said pixel regions containing a photosensitive element, wherein said field isolation region includes an isolation trench, said isolation trench further including a first dielectric material forming sidewalls of said isolation trench and provided on a bottom of said isolation trench, and a second dielectric material situated within said sidewalls and provided over said first dielectric material, said first dielectric material being different than said second dielectric material; and    a doped region formed within said first region and below said isolation trench, said doped region being of said predefined conductivity type and having a doping concentration higher than a doping concentration of said first region, wherein additional dopants in said doped region causing said higher dopant concentration are displaced away from said separated active pixel regions by said sidewalls being arranged and configured to mask said substrate from said additional dopants.    
   
   
       80 . The imaging device of  claim 79 , wherein the first dielectric material has a thickness of at least about one hundred angstroms.  
   
   
       81 . The imaging device of  claim 79 , wherein the doped region extends into the substrate to a depth in a range of about 10 to 100 percent the depth of said isolation trench.  
   
   
       82 . The imaging device of  claim 79 , wherein the doped region extends into the substrate to a depth in a range of about 20 to 80 percent the depth of said isolation trench.  
   
   
       83 . The imaging device of  claim 79 , wherein said thickness of said sidewalls is sufficient to block said additional dopants from becoming implanted in the substrate near said active pixel regions, the doped region having an implanted ion profile in which implanted ions are displaced from an alignment with said active pixel regions by masking due to said sidewall thickness.  
   
   
       84 . The imaging device of  claim 79 , wherein the doped region includes respective shallow implanted dopants and deep implanted dopants.  
   
   
       85 . The imaging device of  claim 84 , wherein the shallow implanted dopants establish a field threshold voltage, and wherein the deep implanted dopants are implanted into the substrate to a depth in a range of about 10 to 100 percent the depth of said isolation trench.  
   
   
       86 . The imaging device of  claim 84 , wherein the shallow implanted dopants and deep implanted dopants have a conductivity type that is the same as the substrate.  
   
   
       87 . An integrated circuit comprising: 
 a semiconductor substrate including a first region of a predefined conductivity type;    a field isolation region for separating said first region into at least two active pixel regions, each containing a photosensitive element, wherein said field isolation region includes an isolation trench, said isolation trench further including a first dielectric material forming sidewalls of said isolation trench and provided on a bottom of said isolation trench, and a second dielectric material situated within said sidewalls and provided over said first dielectric material, said first dielectric material being different than said second dielectric material; and    a doped region formed within said first region and below said isolation trench, said doped region being of said predefined conductivity type and having a doping concentration higher than a doping concentration of said first region, wherein additional dopants in said doped region causing said higher dopant concentration are displaced away from said separated active pixel regions by said sidewalls being arranged and configured to mask said substrate from said additional dopants.