Jitter generation circuit and semiconductor device

Abstract

A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock generation circuit using a current control oscillator (ICO), a differential signal to which a spread spectrum modulation signal, the period or amplitude of which changes, is added is generated, and the differential signal is applied to the ICO and a clock is generated.

1 . A jitter generation circuit for inputting a reference input signal the voltage level of which changes in a constant period and outputting the reference input signal after adding a jitter thereto, the jitter generation circuit comprising a circuit for changing an output to a first level or a second level in accordance with the reference input signal, wherein the circuit is formed so as to be capable of changing the threshold voltage and an output signal with a jitter added is output by changing the threshold voltage.  
     
     
         2 . A jitter generation circuit, as set forth in  claim 1 , wherein a hysteresis inverter circuit having the hysteresis characteristic, an inverter circuit not having the hysteresis characteristic, and a switch circuit provided between an output terminal for outputting the output signal and the hysteresis inverter circuit and between the output terminal and the inverter circuit respectively are comprised and the switch circuit switches the connections so that either the hysteresis inverter circuit or the inverter circuit is connected to the output terminal.  
     
     
         3 . A jitter generation circuit, as set forth in  claim 1 , wherein a hysteresis inverter circuit consisting of a plurality of transistors and a switch for cutting off the transistors, which are provided in order to confer hysteresis on the hysteresis inverter circuit, from the hysteresis inverter circuit are comprised.  
     
     
         4 . A jitter generation circuit, as set forth in  claim 1 , wherein a plurality of gate circuits with different threshold voltages are connected in parallel and any one of the gate circuits is selectively connected to the output terminal by a switch circuit provided between an output terminal for outputting the output signal and each gate circuit.  
     
     
         5 . A semiconductor device comprising the jitter generation circuit set forth in  claim 1  and an internal circuit which operates based on an output signal output from the jitter generation circuit.  
     
     
         6 . A semiconductor device, as set forth in  claim 5 , wherein a clock generation circuit for generating a clock signal as the reference input signal and a circuit provided between the clock generation circuit and the jitter generation circuit and which changes the shape of the clock signal changing in a rectangular wave form to a sinusoidal wave form.  
     
     
         7 . A semiconductor device, as set forth in  claim 5 , wherein a clock generation circuit for generating a clock signal as the reference input signal and a selection signal generation circuit for generating a selection signal based on the reference input signal generated in the clock generation circuit are comprised and the threshold voltages are switched by the selection signal.  
     
     
         8 . A semiconductor device comprising the jitter generation circuit set forth in  claim 1 , a first internal circuit to which a clock signal to be an input signal to the jitter generation circuit is supplied, and a second internal circuit the operation timing of which is less strict than that of the first internal circuit and to which a clock signal with a jitter added in the jitter generation circuit is supplied.  
     
     
         9 . A semiconductor device comprising a jitter generation circuit for inputting a clock signal and outputting the clock signal after adding a jitter thereto, a first internal circuit to which a lock signal to be an input signal to the jitter generation circuit is supplied, and a second internal circuit the operation timing of which is less strict than that of the first internal circuit and to which a clock signal, with a jitter added in the jitter generation circuit, is supplied.  
     
     
         10 . A semiconductor device, as set forth in  claim 8 , wherein a dividing circuit is comprised for generating and inputting to the jitter generation circuit a second clock signal, the frequency of which is lower than that of a first clock signal, by dividing the first clock signal which is used to operate the first internal circuit.  
     
     
         11 . A semiconductor device, as set forth in  claim 8 , wherein a plurality of the jitter generation circuits are comprised and the amount of jitter to be added to a clock signal is made differ from each other in each jitter generation circuit.  
     
     
         12 . A semiconductor device, as set forth in  claim 8 , wherein the jitter generation circuit has a function for adjusting the amount of jitter to be added to a clock signal in accordance with the condition of operation of the internal circuit.  
     
     
         13 . A semiconductor device, as set forth in  claim 12 , wherein the amount of jitter in the jitter generation circuit is adjusted in accordance with the power supply voltage to the internal circuit.  
     
     
         14 . A semiconductor device, as set forth in  claim 12 , wherein the amount of jitter in the generation circuit is adjusted in accordance with the operation speed of the internal circuit.  
     
     
         15 . A semiconductor device, as set forth in  claim 11 , wherein a first jitter generation circuit for adding a jitter to a clock signal and a second jitter generation circuit for further adding a jitter to the clock signal with the jitter added are comprised.  
     
     
         16 . A semiconductor device, as set forth in  claim 11 , wherein a first jitter generation circuit and a second jitter generation circuit to which a clock signal the frequency of which is lower than the first jitter generation circuit is input are comprised and the second jitter generation circuit adds a jitter larger than that of the first jitter generation circuit.