Internal clock generator

Abstract

An internal clock generator that modulates a high-frequency clock signal to a low-frequency signal to transmit the low-frequency signal if a transmission line for transmitting the high-frequency clock signal is long, and then restores the transmitted low-frequency signal to the high-frequency signal. The internal clock generator includes a first signal generation unit for receiving a first signal having a first frequency and generating a second signal having a second frequency that is lower than the first frequency, and a second signal generation unit for receiving the second signal and generating a third signal having a frequency equal to the first frequency. Here, the third signal is used as a signal for controlling an operating time point of an internal circuit of a synchronous memory device.

1 . An internal clock generator comprising: 
 a first signal generation unit for receiving a first signal having a first frequency and generating a second signal having a second frequency that is lower than the first frequency; and    a second signal generation unit for receiving the second signal and generating a third signal having a frequency equal to the first frequency.    
   
   
       2 . The internal clock generator as claimed in  claim 1 , wherein the third signal is used as a signal for controlling an operating time point of an internal circuit of a synchronous memory device.  
   
   
       3 . An internal clock generator comprising: 
 a frequency modulation unit for receiving a first clock signal having a first frequency and outputting second and third clock signal having a second frequency; and    a clock generation unit for receiving the second and third clock signals and outputting a fourth clock signal having the first frequency.    
   
   
       4 . The internal clock generator as claimed in  claim 3 , wherein if the first frequency is fo, the second frequency becomes fo/2.  
   
   
       5 . The internal clock generator as claimed in  claim 4 , wherein a rising edge of the second clock signal is in synchronization with a rising edge of the first clock signal, and a rising edge of the third clock signal is in synchronization with a falling edge of the first clock signal.  
   
   
       6 . The internal clock generator as claimed in  claim 5 , wherein a high-level period of the second and third clock signals is equal to a period of the first clock signal.  
   
   
       7 . The internal clock generator as claimed in  claim 3 , wherein the first frequency is the same as a frequency of an external clock applied to a synchronous memory device.  
   
   
       8 . The internal clock generator as claimed in  claim 7 , wherein the fourth clock signal is applied to an internal circuit of the synchronous memory device and controls an operating time point of the internal circuit.  
   
   
       9 . The internal clock generator as claimed in  claim 8 , wherein a transmission distance of the second and third clock signals that reach the clock generation unit is longer than a transmission distance of the fourth clock signal that reaches the internal circuit.