Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories

Abstract

A process manufactures an interpoly dielectric layer for non-volatile memory cells of a semiconductor device with an interpoly dielectric layer. The process begins with forming the tunnel oxide, and hence the amorphous or polycrystalline silicon layer, using conventional techniques. After the amorphous or polycrystalline silicon layer is surface cleansed and passivated, the surface of the polycrystalline layer is nitrided directly by using radical nitrogen. This is followed by the formation of the interpoly dielectric, either as an ONO layer or a single silicon layer, by means of the CVD technique. Masking to define the floating gate may be performed immediately before or after the direct nitridation step is carried out. The equivalent electrical thickness of the interpoly dielectric, obtained by combining the nitride oxide layer and by the following dielectric, does not exceed 130 Angstroms in either the ONO layer or the single silicon layer embodiment.

1 . A process for manufacturing a non-volatile memory cell of a semiconductor device, comprising: 
 depositing a thin oxide layer onto a semiconductor substrate;    depositing a silicon layer onto said thin oxide layer to form a floating gate region of the memory cell; and    directly nitriding a surface of said silicon layer, using radical nitrogen, thereby forming a thin layer of silicon nitride oxide thereon;    depositing a silicon oxide layer directly on the silicon nitride oxide layer; and    forming a control gate directly on the silicon oxide layer.    
   
   
       2 . A process according to  claim 1 , wherein the thickness of the silicon nitride oxide layer, formed by the directly nitriding step, varies between 0.5 to 5.0 nm.  
   
   
       3 . A process according to  claim 1 , wherein a nitrogen distribution inside the silicon nitride oxide layer, formed by the directly nitriding step, is no less than 1 e22 at/cm 3  as peak value, for a total amount of no less than 1 e15 at/cm 2 .  
   
   
       4 . A process according to  claim 1 , wherein the silicon oxide layer is formed, on either batch or single wafers systems, subsequently to said directly nitriding step.  
   
   
       5 . A process according to  claim 1 , wherein a masking step to define the floating gate region of the cell and a step of dry etching the silicon layer are carried out immediately before said directly nitriding step.  
   
   
       6 . A process according to  claim 1  wherein a masking step to define the floating gate region of the cell and a step of dry etching the silicon layer are carried out immediately after the directly nitriding step.  
   
   
       7 . A process according to  claim 1 , wherein the silicon nitride oxide and silicon oxide layers together have a thickness that is equal to or less than 130 Angstroms.  
   
   
       8 . A process according to  claim 7 , further comprising densifying said silicon oxide layer by heat treatment under an N 2 , H 2 O and O 2  atmosphere.  
   
   
       9 . A process for manufacturing a non-volatile memory cell of a semiconductor device, comprising: 
 forming a thin dielectric layer on a semiconductor substrate;    forming a first conductive layer on said thin dielectric layer, the first conductive layer forming a floating gate region having an entire top surface;    directly nitriding a surface of the first conductive layer, using radical nitrogen, thereby forming a barrier layer on the entire top surface of the floating gate region;    forming interlevel dielectric layer on the barrier layer, wherein the interpoly dielectric is formed above the barrier layer and includes only a single layer of silicon oxide; and    forming a second conductive layer directly on the interlevel dielectric layer.    
   
   
       10 . The process of  claim 9 , wherein the barrier layer includes silicon nitride oxide having a thickness between 0.5 to 5.0 nm.  
   
   
       11 . The process of  claim 9 , wherein the barrier layer includes silicon nitride oxide having a nitrogen distribution of no less than 1e22 at/cm 3  as peak value, for a total amount of no less than 1 e15 at/cm 2 .  
   
   
       12 . The process of  claim 9 , wherein the interlevel dielectric layer is formed after forming the barrier layer.  
   
   
       13 . The process of  claim 9 , further comprising defining the first conductive layer to form the floating gate region of the memory cell immediately before forming the barrier layer.  
   
   
       14 . The process of  claim 9 , further comprising defining the first conductive layer to form the floating gate region of the memory cell immediately after forming the barrier layer.  
   
   
       15 . The process of  claim 9 , wherein the single layer of silicon oxide is formed by CVD.  
   
   
       16 . A non-volatile memory cell, comprising: 
 a tunnel dielectric layer positioned on a semiconductor substrate that includes source and drain regions;    a floating gate formed on the tunnel dielectric layer;    an interlevel dielectric layer positioned above the floating gate region, the interlevel dielectric layer including only a single silicon oxide layer;    a control gate region positioned above the interlevel dielectric layer; and    a barrier layer of silicon nitride oxide formed between the floating gate region and the interlevel dielectric layer, the barrier layer having a thickness between 0.5 to 5.0 nm.    
   
   
       17 . The memory cell of  claim 16 , wherein the barrier layer is directly above and contacts a top surface of the floating gate.  
   
   
       18 . The memory cell of  claim 17  wherein the single silicon oxide layer directly contacts the barrier layer and directly contacts the control gate region.  
   
   
       19 . The memory cell of  claim 16 , wherein the barrier layer intervenes between the interlevel dielectric layer and the floating gate such that no portion of the floating gate contacts the interlevel dielectric layer.  
   
   
       20 . The memory cell of  claim 16 , wherein the barrier layer includes silicon nitride oxide having a nitrogen distribution of no less than 1 e22 at/cm 3  as peak value, for a total amount of no less than 1 e15 at/cm 2 .