System and method for vertically stacking computer memory components

Abstract

System and method for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One embodiment provides a chip stack where two smaller chips are interconnected to a larger third chip on both sides thereof with the lower smaller chip flipped and connected below the larger chip. Further, in another embodiment, interconnecting structures extend from the larger chip beyond the extent of the lower smaller chip to facilitate the electronic connection of the chip stack with other computer components or circuit board. Another embodiment provides a method for stacking chips where two smaller chips are interconnected to a larger third chip on both sides thereof with the lower smaller chip flipped and connected below the larger chip.

1 - 21 . (canceled)  
   
   
       43 . A chip stack comprising: 
 a first chip having a first and a second side, wherein a first plurality of contacts are formed on the first side in a first pattern and a second plurality of contacts are formed on the second side in a second pattern;    a second chip having a first and a second side, wherein the first side of the second chip includes a first plurality of contacts arranged in the first pattern, wherein the second chip is located proximate the first side of the first chip, and wherein the second chip is positioned so that the first plurality of contacts on the second chip are aligned with the first plurality of contacts on the first chip;    a third chip having a first and a second side wherein the third chip includes a first plurality of contacts arranged in the second pattern on the first side wherein the third chip is located proximate the second side of the first chip such that the first chip is interposed between the second and third chips and so that the first plurality of contacts on the third chip are aligned with the second plurality of contacts on the first chip;    a first set of interconnecting structures having a first length that are interposed between the first plurality of contacts on the first chip and the first plurality of contacts on the second chip so as to interconnect the first plurality of contacts on the first chip and the first plurality of contacts on the second chip; and    a second set of interconnecting structures having a second length that are interposed between the second plurality of contacts on the first chip and the first plurality of contacts on the third chip so as to interconnect the second plurality of contacts on the first chip and the first plurality of contacts on the third chip.    
   
   
       44 . The chip stack of  claim 43 , wherein the first pattern is a substantially similar pattern as the second pattern.  
   
   
       45 . The chip stack of  claim 43 , wherein the first chip further comprises a third plurality of contacts arranged in a third pattern on the second side.  
   
   
       46 . The chip stack of  claim 45 , further comprising a third set of interconnecting structures having the second length interconnected to the third plurality of contacts.  
   
   
       47 . The chip stack of  claim 46 , wherein the first chip and the third set of interconnecting structures are arranged in a modular unit defining an interstitial space around the third chip.  
   
   
       48 . The chip stack of  claim 46 , wherein the first chip defines a platform over the third chip and wherein the third set of interconnecting structures define side struts supporting the platform.  
   
   
       49 . The chip stack of  claim 46 , wherein the first chip and the third set of interconnecting structures are arranged in contiguous non-conductive material.  
   
   
       50 . The chip stack of  claim 46 , wherein the first chip and the third set of interconnecting structures define a carrier for positioning one or more chips above the second chip.  
   
   
       51 . The chip stack of  claim 46 , wherein the first chip and the third set of interconnecting structures are arranged within a modular unit that can accept one or more chips, and the modular unit further provides an interstitial space around the third chip.  
   
   
       52 . The chip stack of  claim 46 , wherein the first chip comprises a preformed support structure.  
   
   
       53 . A method of stacking chips comprising: 
 providing a first chip having a first and a second side, wherein a first plurality of contacts are formed on the first side in a first pattern and a second plurality of contacts are formed on the second side in a second pattern;    providing a second chip having a first and a second side, wherein the first side of the second chip includes a first plurality of contacts arranged in the first pattern, wherein the second chip is located proximate the first side of the first chip, and wherein the second chip is positioned so that the first plurality of contacts on the second chip are aligned with the first plurality of contacts on the first chip;    providing a third chip having a first and a second side wherein the third chip includes a first plurality of contacts arranged in the second pattern on the first side, and wherein the third chip is located proximate the second side of the first chip such that the first chip is interposed between the second and third chips and so that the first plurality of contacts on the third chip are aligned with the second plurality of contacts on the first chip;    providing a first set of interconnecting structures having a first length that are interposed between the first plurality of contacts on the first chip and the first plurality of contacts on the second chip so as to interconnect the first plurality of contacts on the first chip and the first plurality of contacts on the second chip; and    providing a second set of interconnecting structures having a second length that are interposed between the second plurality of contacts on the first chip and the first plurality of contacts on the third chip so as to interconnect the second plurality of contacts on the first chip and the first plurality of contacts on the third chip.    
   
   
       54 . The method of stacking chips of  claim 53 , wherein the first pattern is a substantially similar pattern as the second pattern.  
   
   
       55 . The method of stacking chips of  claim 53 , wherein the first chip further comprises a third plurality of contacts arranged in a third pattern on the second side.  
   
   
       56 . The method of stacking chips of  claim 55 , further comprising providing a third set of interconnecting structures having a third length interconnected to the third plurality of contacts.  
   
   
       57 . The method of stacking chips of  claim 56 , wherein the first chip and the third set of interconnecting structures are arranged in a modular unit defining an interstitial space around the third chip.  
   
   
       58 . The method of stacking chips of  claim 56 , wherein the first chip defines a platform over the third chip and wherein the third set of interconnecting structures define side struts supporting the platform.  
   
   
       59 . The method of stacking chips of  claim 56 , wherein the first chip and the third set of interconnecting structures are arranged in contiguous non-conductive material.  
   
   
       60 . The method of stacking chips of  claim 56 , wherein the first chip and the third set of interconnecting structures define a carrier for positioning one or more chips above the second chip.  
   
   
       61 . The method of stacking chips of  claim 56 , wherein the first chip and the third set of interconnecting structures are arranged within a modular unit that can accept one or more chips, and the modular unit further provides an interstitial space around the third chip.  
   
   
       62 . A chip stack comprising: 
 a first chip having a first and a second side, wherein a first plurality of contacts are formed on the first side in a first pattern and a second plurality of contacts are formed on the second side in a second pattern;    a second chip having a first and a second side and a selected thickness, wherein the first side of the second chip includes a first plurality of contacts arranged in the first pattern, wherein the second chip is located proximate the first side of the first chip, and wherein the second chip is positioned so that the first plurality of contacts on the second chip are aligned with the first plurality of contacts on the first chip;    a third chip having a first and a second side wherein the third chip includes a first plurality of contacts arranged in the second pattern on the first side wherein the third chip is located proximate the second side of the first chip such that the first chip is interposed between the second and third chips and so that the first plurality of contacts on the third chip are aligned with the second plurality of contacts on the first chip;    means for interconnecting the first plurality of contacts on the first chip and the first plurality of contacts on the second chip; and    means for interconnecting the second plurality of contacts on the first chip and the first plurality of contacts on the third chip, wherein the first chip is interposed between the first side of the second chip and the first side of the third.