Jitter producing circuitry and methods

Abstract

To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

1 . A method of adding jitter to a clock signal comprising: 
 delaying successive cycles of the clock signal by a cyclically changing amount; and    cyclically changing the amount of delay by changing the number of unit delay increments.    
   
   
       2 . The method defined in  claim 1  wherein the cyclically changing comprises: 
 controlling frequency of the cyclically changing amount of delay.    
   
   
       3 . The method defined in  claim 1  wherein the cyclically changing comprises: 
 controlling amplitude of the cyclically changing amount of delay.    
   
   
       4 . The method defined in  claim 2  wherein the controlling frequency is at least partly responsive to frequency of the clock signal.  
   
   
       5 . The method defined in  claim 4  wherein the controlling frequency comprises: 
 dividing the frequency of the clock signal by a divisor parameter.    
   
   
       6 . The method defined in  claim 5  wherein the divisor parameter is variable.  
   
   
       7 . The method defined in  claim 2  wherein controlling the frequency comprises: 
 selecting a rate for cyclically changing the amount of delay by the plurality of unit delay increments.    
   
   
       8 . The method defined in  claim 3  wherein the controlling amplitude is at least partly responsive to an amplitude parameter.  
   
   
       9 . The method defined in  claim 8  wherein the amplitude parameter is variable.  
   
   
       10 . Apparatus for adding jitter to a clock signal comprising: 
 means for delaying successive cycles of the clock signal by a cyclically changing amount; and    means for cyclically changing the amount of delay by changing the number of unit delay increments.    
   
   
       11 . The apparatus defined in  claim 10  wherein the means for cyclically changing comprises: 
 means for controlling frequency of the cyclically changing amount of delay.    
   
   
       12 . The apparatus defined in  claim 11  wherein the means for controlling frequency comprises: 
 means for selecting a rate for cyclically changing the amount of delay by the plurality of unit delay increments.    
   
   
       13 . The apparatus defined in  claim 10  wherein the means for cyclically changing comprises: 
 means for controlling amplitude of the cyclically changing amount of delay.    
   
   
       14 . The apparatus defined in  claim 11  wherein the means for controlling frequency is at least partly responsive to frequency of the clock signal.  
   
   
       15 . The apparatus defined in  claim 14  wherein the means for controlling frequency comprises: 
 means for dividing the frequency of the clock signal by a divisor parameter.    
   
   
       16 . The apparatus defined in  claim 15  wherein the divisor parameter is variable.  
   
   
       17 . The apparatus defined in  claim 13  wherein the means for controlling amplitude is at least partly responsive to an amplitude parameter.  
   
   
       18 . The apparatus defined in  claim 17  wherein the amplitude parameter is variable.  
   
   
       19 . Apparatus for adding jitter to a clock signal comprising: 
 delay circuitry that delays successive cycles of the clock signal by a cyclically changing amount; and    control circuitry that cyclically changes the amount of delay by changing the number of unit delay increments.    
   
   
       20 . The apparatus defined in  claim 19  wherein the control circuitry comprises: 
 frequency control circuitry that controls frequency of the cyclically changing amount of delay.    
   
   
       21 . The apparatus defined in  claim 20  wherein the frequency control circuit comprises: 
 circuitry that selects a rate for cyclically changing the amount of delay by the plurality of unit delay increments.    
   
   
       22 . The apparatus defined in  claim 19  wherein the control circuitry comprises: 
 amplitude control circuitry that controls amplitude of the cyclically changing amount of delay.    
   
   
       23 . The apparatus defined in  claim 20  wherein the frequency control circuitry is at least partly responsive to frequency of the clock signal.  
   
   
       24 . The apparatus defined in  claim 23  wherein the frequency control circuitry comprises: 
 frequency dividing circuitry that divides the frequency of the clock signal by a divisor parameter.    
   
   
       25 . The apparatus defined in  claim 24  wherein the divisor parameter is variable.  
   
   
       26 . The apparatus defined in  claim 22  wherein the amplitude control circuitry is at least partly responsive to an amplitude parameter.  
   
   
       27 . The apparatus defined in  claim 26  wherein the amplitude parameter is variable.