Electrically stabilized integrated circuit

Abstract

An integrated electronic circuit comprises active components disposed on the surface of a substrate and connected by electrical connections disposed within a metallization level. A dielectric material situated between the surface of the substrate and the metallization level, or in the metallization level, has a locally higher value of dielectric permittivity so as to selectively increase a capacitance between certain portions of the active components or of the connections. An electrical state of the circuit in operation is then stabilized, thanks to a higher electrical charge carried by the portions of the active components or of the connections whose capacitance is enhanced. The circuit can be a static random access memory cell.

1 . An integrated electronic circuit comprising: 
 a substrate having a surface;    active components disposed on the surface of the substrate;    electrical connections disposed within a metallization level situated above the surface of the substrate, the electrical connections being connected to the active components; and    a dielectric material situated between the surface of the substrate and the metallization level, or in the metallization level, the dielectric material having a locally higher value of dielectric permittivity so as to selectively increase a capacitance between certain portions of the active components or of the connections.    
   
   
       2 . The circuit according to  claim 1 , wherein the increased capacitance is present between, first, a gate of a MOS transistor or a connection linking a gate of a MOS transistor and, second, another portion of one of the active components or of connection of the circuit.  
   
   
       3 . The circuit according to  claim 1 , wherein the dielectric material locally exhibits a different chemical composition between the portions of the active components or of the connections of the circuit for which the capacitance is increased.  
   
   
       4 . The circuit according to  claim 1 , wherein the active components include two access transistors and two inverters of a static random access memory cell, 
 each inverter having an input comprising a gate link between respective gates of two MOS transistors of said inverter, and being connected between a voltage reference terminal and voltage supply terminal, the gate link of each inverter being situated at the surface of the substrate and connected to a section of interconnect disposed within the metallization layer situated above said surface of the substrate, said section of interconnect being furthermore connected to an output of one of the access transistors and to an output of the other inverter,    each access transistor additionally having an input connected to a bit line, and a gate situated at the surface of the substrate and connected to a word line, wherein the dielectric material includes:    an intermediate layer situated between the surface of the substrate and the metallization layer comprising at least a first portion and at least a second portion respectively of a first dielectric material within a first region and of a second dielectric material within a second region, said first dielectric material having a higher dielectric permittivity than a dielectric permittivity of said second dielectric material,    wherein the gate link of each inverter is separated from the voltage reference terminal and from the voltage supply terminal of said inverter, and also from the section of interconnect of the other inverter by respective gaps situated mainly within the first region, and    wherein the gate and the input of each access transistor is situated within the second region.    
   
   
       5 . The circuit according to  claim 4 , wherein the gate link of each inverter is substantially adjacent to the voltage reference terminal and/or to the voltage supply terminal of said inverter, in a projection onto the surface of the substrate.  
   
   
       6 . The circuit according to  claim 4 , wherein each voltage reference terminal or voltage supply terminal comprises a connection that is substantially perpendicular to the surface of the substrate and that extends through the intermediate layer in the first substrate region.  
   
   
       7 . The circuit according to  claim 4 , wherein each gate link of one of the inverters is substantially adjacent to the section of interconnect to which the gate link of the other inverter is connected, in a projection onto the surface of the substrate.  
   
   
       8 . The circuit according to  claim 4 , wherein each interconnect section of an inverter is connected to the output of the corresponding access transistor and to the output of the other inverter by respective connections that are substantially perpendicular to the surface of the substrate and that extend through the intermediate layer in the first region.  
   
   
       9 . The circuit according  claim 4 , wherein the first dielectric material is selected from the list comprising alumina, barium, strontium and titanium oxide, beryllium aluminum oxide, cerium oxide, hafnium oxide, hafnium silicate, lanthanum oxide, silicon nitride, titanium oxide, tantalum oxide, yttrium oxide, zirconium oxide and zirconium silicate, or is a mixture comprising at least one of said materials, and wherein the second dielectric material is selected from the list comprising silica, an organic material and a fluorinated material, or is a mixture comprising at least one of the latter materials.  
   
   
       10 . The circuit according to  claim 4 , wherein the metallization layer itself comprises a first portion and a second portion respectively of a third dielectric material in the first region and of a fourth dielectric material in the second region, said third dielectric material having a higher dielectric permittivity than a dielectric permittivity of said fourth dielectric material.  
   
   
       11 . The circuit according to  claim 10 , wherein the third dielectric material is selected from the list comprising alumina, barium, strontium and titanium oxide, beryllium aluminum oxide, cerium oxide, hafnium oxide, hafnium silicate, lanthanum oxide, silicon nitride, titanium oxide, tantalum oxide, yttrium oxide, zirconium oxide and zirconium silicate, or is a mixture comprising at least one of said materials, and wherein the fourth dielectric material is selected from the list comprising silica, an organic material and a fluorinated material, or is a mixture comprising at least one of the latter materials.  
   
   
       12 . The circuit according to  claim 4 , additionally comprising a stop layer disposed over the gate lines, on at least one side of each of said gate lines opposite to the substrate, and wherein said stop layer itself comprises a first portion and a second portion respectively of a first stopping material in the first region and of a second stopping material in the second region, said first stopping material having a higher dielectric permittivity than a dielectric permittivity of said second stopping material.  
   
   
       13 . A memory array comprising: 
 first and second SRAM cells disposed next to one another on a surface of a substrate, wherein each of the SRAM cells includes:    two access transistors and two inverters, each access transistor having an input connected to a bit line, and a gate situated at the surface of the substrate and connected to a word line, each inverter including: 
 two MOS transistors connected between a voltage reference terminal and voltage supply terminal;  
 an input comprising a gate link between respective gates of the two MOS transistors, the gate link of each inverter being situated at the surface of the substrate; and  
 a section of interconnect connected to the gate link and disposed within a metallization layer situated above said surface of the substrate, said section of interconnect being furthermore connected to an output of one of the access transistors and to an output of the other inverter; and  
   an intermediate layer situated between the surface of the substrate and the metallization layer comprising at least a first portion and at least a second portion respectively of a first dielectric material within a first region and of a second dielectric material within a second region, said first dielectric material having a higher dielectric permittivity than a dielectric permittivity of said second dielectric material,    wherein the gate link of each inverter is separated from the voltage reference terminal and from the voltage supply terminal of said inverter, and also from the section of interconnect of the other inverter by respective gaps situated mainly within the first region, and    wherein the gate and the input of each access transistor is situated within the second region, wherein the cells are arranged so that the first regions, respectively corresponding to several cells, are contiguous with one another, and so that the second regions, respectively corresponding to certain of the cells, are also contiguous with one another.    
   
   
       14 . The memory array of  claim 13 , wherein the gate link of each inverter is substantially adjacent to the voltage reference terminal and/or to the voltage supply terminal of said inverter, in a projection onto the surface of the substrate.  
   
   
       15 . The memory array of  claim 13 , wherein each voltage reference terminal or voltage supply terminal comprises a connection that is substantially perpendicular to the surface of the substrate and that extends through the intermediate layer in the first substrate region.  
   
   
       16 . The memory array of  claim 13 , wherein each gate link of one of the inverters is substantially adjacent to the section of interconnect to which the gate link of the other inverter is connected, in a projection onto the surface of the substrate.  
   
   
       17 . The memory array of  claim 13 , wherein each interconnect section of an inverter is connected to the output of the corresponding access transistor and to the output of the other inverter by respective connections that are substantially perpendicular to the surface of the substrate and that extend through the intermediate layer in the first region.  
   
   
       18 . The memory array of  claim 13 , wherein the first dielectric material is selected from the list comprising alumina, barium, strontium and titanium oxide, beryllium aluminum oxide, cerium oxide, hafnium oxide, hafnium silicate, lanthanum oxide, silicon nitride, titanium oxide, tantalum oxide, yttrium oxide, zirconium oxide and zirconium silicate, or is a mixture comprising at least one of said materials, and wherein the second dielectric material is selected from the list comprising silica, an organic material and a fluorinated material, or is a mixture comprising at least one of the latter materials.  
   
   
       19 . The memory array of  claim 13 , wherein the metallization layer itself comprises a first portion and a second portion respectively of a third dielectric material in the first region and of a fourth dielectric material in the second region, said third dielectric material having a higher dielectric permittivity than a dielectric permittivity of said fourth dielectric material.  
   
   
       20 . The memory array of  claim 19 , wherein the third dielectric material is selected from the list comprising alumina, barium, strontium and titanium oxide, beryllium aluminum oxide, cerium oxide, hafnium oxide, hafnium silicate, lanthanum oxide, silicon nitride, titanium oxide, tantalum oxide, yttrium oxide, zirconium oxide and zirconium silicate, or is a mixture comprising at least one of said materials, and wherein the fourth dielectric material is selected from the list comprising silica, an organic material and a fluorinated material, or is a mixture comprising at least one of the latter materials.  
   
   
       21 . The memory array of  claim 13 , additionally comprising a stop layer disposed over the gate lines, on at least one side of each of said gate lines opposite to the substrate, and wherein said stop layer itself comprises a first portion and a second portion respectively of a first stopping material in the first region and of a second stopping material in the second region, said first stopping material having a higher dielectric permittivity than a dielectric permittivity of said second stopping material.  
   
   
       22 . An integrated electronic circuit fabrication process, comprising the following steps: 
 forming active components at a surface level of a semiconductor substrate;    depositing, over the substrate surface, at least one layer of a dielectric material;    locally modifying the dielectric material, so as to selectively increase a capacitance between certain portions of active components or of circuit connections; and    forming the circuit connections.    
   
   
       23 . The process according to  claim 22 , wherein the step for modifying the dielectric material comprises a replacement of a portion of said dielectric material with a portion of another material having a different chemical composition, in a region of the layer intended to contain, or to be adjacent to, the portions of the active components or of the connections whose capacitance is to be enhanced.  
   
   
       24 . The process according to  claim 22 , wherein the integrated electronic circuit comprises an integrated static random access memory cell, the process comprising the following steps: 
 forming, on the surface of the semiconductor substrate, MOS transistors of two inverters, two MOS access transistors and, for each inverter, a link connecting gates of the transistors of said inverter, the active components including the inverters and the MOS access transistors;    forming, over the substrate, a first portion of an intermediate layer in a first region so as to at least partially surround the gate links of the transistors of the inverters in a plane parallel to the surface of the substrate, and a second portion of the intermediate layer in a second region so as to at least partially surround gates and inputs of the access transistors, the first and second portions of the intermediate layer being respectively of a first and a second dielectric material, said first dielectric material having a dielectric permittivity that is higher than a dielectric permittivity of said second dielectric material;    forming, through the intermediate layer, connections that are substantially perpendicular to the surface of the substrate and that respectively extend as far as source or drain regions of the transistors or as far as the gate links; and    forming, over the intermediate layer, a metallization layer incorporating two sections of interconnect each connected to the gate link of the transistors of one of the inverters and to an output of the other inverter, voltage reference terminals, voltage supply terminals and cell access terminals, so that said sections of interconnect and said terminals are in electrical contact with respective connections of the intermediate layer,    the section of interconnect and the voltage reference terminal and voltage supply terminal of each inverter being disposed within the metallization layer so as to be separated from the gate link of the other inverter by respective gaps situated mainly within the first substrate region,    and the cell access terminals being disposed within the metallization layer substantially in a vertical line with the inputs of the access transistors with respect to the surface of the substrate.    
   
   
       25 . The process according to  claim 24 , wherein forming the intermediate layer comprises the following sub-steps: 
 depositing a layer of the second dielectric material over the surface of the substrate in the first region and in the second region of the substrate;    forming a mask over the layer of the second dielectric material, said mask having an opening corresponding to the first region;    removing the second dielectric material in the first region through the opening in the mask, so that a residual portion of second dielectric material remains in the second region;    forming a portion of the first dielectric material in the first region; and    polishing the respective portions of first and second dielectric materials so that said portions have respective thicknesses that are substantially equal in a direction perpendicular to the surface of the substrate.    
   
   
       26 . The process according to  claim 24 , wherein forming the metallization layer comprises the following sub-steps: 
 depositing a layer of a third dielectric material over the intermediate layer in the first region and second region of the substrate, on a side of said intermediate layer opposite to the substrate;    forming a first mask over the layer of the third dielectric material, said first mask having an opening corresponding to the first region;    removing the third dielectric material in the first region through the opening in the first mask, so that a residual portion of third dielectric material remains in the second region; and    forming a portion of a fourth dielectric material in the first region,    said fourth dielectric material having a dielectric permittivity that is higher than a dielectric permittivity of said third dielectric material.    
   
   
       27 . The process according to  claim 26 , wherein forming the intermediate layer comprises the following sub-steps: 
 depositing a layer of the second dielectric material over the surface of the substrate in the first region and in the second region of the substrate;    forming a second mask over the layer of the second dielectric material, said second mask having an opening corresponding to the first region;    removing the second dielectric material in the first region through the opening in the second mask, so that a residual portion of second dielectric material remains in the second region;    forming a portion of the first dielectric material in the first region; and    polishing the respective portions of first and second dielectric materials so that said portions have respective thicknesses that are substantially equal in a direction perpendicular to the surface of the substrate, whereby the first and second masks are formed by photolithography using the same photomask.    
   
   
       28 . The process according to  claim 24 , also comprising, before forming the intermediate layer, covering the surface of the substrate, the transistors and the gate links with a stop layer, said step for covering with the stop layer comprising the following sub-steps: 
 depositing a layer of a first stopping material over the surface of the substrate in the first region and second region;    forming a first mask over the layer of the first stopping material, said first mask having an opening corresponding to the first region;    removing the first stopping material in the first region through the opening in the first mask, so that a residual portion of first stopping material remains in the second region; and    forming a portion of a second stopping material in the first region,    said second stopping material having a dielectric permittivity that is higher than a dielectric permittivity of said first stopping material.    
   
   
       29 . The process according to  claim 28 , wherein forming the intermediate layer comprises the following sub-steps: 
 depositing a layer of the second dielectric material over the surface of the substrate in the first region and in the second region of the substrate;    forming a second mask over the layer of the second dielectric material, said second mask having an opening corresponding to the first region;    removing the second dielectric material in the first region through the opening in the second mask, so that a residual portion of second dielectric material remains in the second region;    forming a portion of the first dielectric material in the first region; and    polishing the respective portions of first and second dielectric materials so that said portions have respective thicknesses that are substantially equal in a direction perpendicular to the surface of the substrate, wherein the first and second masks are formed by photolithography using the same photomask.