Process for producing semiconductor nonvolatile memory cell array

Abstract

A semiconductor nonvolatile memory cell array includes a plurality of semiconductor nonvolatile memory cells. Each memory cell has a control electrode ( 30 ); a pair of impurity diffusion regions ( 21, 22 ) to provide first and second main electrodes; a pair of variable resistance sections ( 24, 26 ); and a pair of charge storage sections ( 50, 52 ). The array has a word line ( 33 ) electrically connected to the control electrodes of the semiconductor nonvolatile memory cells and bit lines provided perpendicular to the word line and composed of the impurity diffusion regions; and layer insulation layers ( 57, 58 ) provided between the charge storage sections and the word line.

1 . A process for producing a semiconductor nonvolatile memory cell array, comprising the steps of: 
 a control electrode forming step for forming a control electrode on an insulation layer of a semiconductor substrate of a first conductive type;    a laminated body forming step for laminating on said semiconductor substrate and said control electrode a bottom silicon oxide layer, a silicon nitride layer, and a top silicon oxide layer to provide a laminated body;    an impurity low density diffusion section forming step for forming an impurity low density diffusion section of a second conductive type;    a variable resistance section forming step for injecting an impurity of a second conductive type into a region of said impurity low density diffusion section spaced from said control electrode to form a pair of impurity diffusion regions that work as first and second main electrodes and form bit lines and a variable resistance section in a region of said impurity low density diffusion section adjacent to said control electrode;    a layer insulation layer accumulating step for accumulating a layer insulation layer on said laminated body; and    a word line forming step for forming a word line that intersects said bit lines and is electrically connected to said control electrode.    
     
     
         2 . The process according to  claim 1 , which further comprises a polishing step for polishing, after said layer insulation layer accumulating step, a top surface of said layer insulation layer so that a top surface of said control electrode is exposed, said laminated body are made into first and second charge storage sections, and that said top surface of said layer insulation layer and said top surface of said control electrode form a continuous plane, wherein said word line is formed in contact with said plane in said word line forming step.  
     
     
         3 . The process according to  claim 1 , wherein said variable resistance section forming step includes a step for making a salicide region of said impurity diffusion region after said impurity diffusion regions are formed.  
     
     
         4 . The process according to  claim 1 , wherein said variable resistance section forming step comprises the steps of: 
 forming a side wall spacer in a region adjacent to said control electrode on said impurity low density diffusion section and    injecting an impurity of a second conductive type into a region spaced from said control electrode to form a pair of impurity diffusion regions that work as first and second main electrodes and a variable resistance section in a region adjacent to said control electrode in said impurity low density diffusion section.    
     
     
         5 . The process according to  claim 1 , wherein said variable resistance section forming step comprises the steps of: 
 forming a first side wall spacer in a region adjacent to said control electrode in said impurity low density diffusion section;    injecting an impurity of said second conductive type in a portion that is not covered by said first side wall spacer to provide a high density diffusion section and a low density diffusion variable resistance section that is covered by said first side wall spacer;    forming a second side wall spacer in a region adjacent to said first side wall spacer on said high density diffusion section; and    injecting an impurity of said second conductive type into a portion that is not covered by said second side wall spacer to provide a pair of impurity diffusion regions to work as first and second main electrodes and a high density diffusion variable resistance section that is covered by the second side wall spacer.    
     
     
         6 . A process for producing a semiconductor nonvolatile memory cell array, comprising the steps of: 
 a control electrode forming step for forming an insulation layer and a control electrode on a semiconductor substrate of a first conductive type;    a mask forming step for forming a hard mask on said control electrode;    an accumulated body forming step for accumulating on said semiconductor substrate and said hard mask a bottom silicon oxide layer, a silicon nitride layer, and a top silicon oxide layer to form an accumulated body;    an impurity low density diffusion section forming step for forming an impurity low density diffusion section of a second conductive type;    a variable resistance section forming step for injecting an impurity of said second conductive type into a region spaced from said control electrode to form a pair of impurity diffusion regions to work as first and second main electrodes and a variable resistance section in a region adjacent to said control electrode on said impurity low density diffusion section after a side wall spacer is provided in a region adjacent to said control electrode on said impurity low density diffusion section;    an oxide layer forming step for forming an oxide layer on said impurity diffusion region; and    a word line forming step for a word line, which intersects said impurity diffusion region used as a bit line, on a plane in contact with said control electrode and said oxide layer.