Semiconductor device and manufacturing method of the same

Abstract

In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n + -type semiconductor region of the protective diode are formed in the same step.

1 . A semiconductor device including a field-effect transistor and a diode formed over the same semiconductor substrate, the semiconductor device comprising: 
 a drain region of said field-effect transistor formed over the semiconductor substrate;    a channel forming region of said field-effect transistor formed over the drain region;    a source region of said field-effect transistor formed over the channel forming region;    a trench reaching the drain region from an upper surface of the source region;    a first insulating film formed in the trench;    a first conductive film formed over the first insulating film in the trench;    a gate insulating film of said field-effect transistor formed over the first insulating film in the trench;    a gate electrode of said field-effect transistor formed over the gate insulating film in the trench;    a second conductive film made of the same film as the first conductive film, and formed over the semiconductor substrate; and    an anode region and a cathode region of the diode formed in the second conductive film,    wherein each of the anode region and the cathode region of the diode is electrically connected to the gate electrode or the source region of the field-effect transistor.    
   
   
       2 . The semiconductor device according to  claim 1 , 
 wherein a plurality of cathode regions are formed in the second conductive film,    wherein said anode region is disposed in contact with the plurality of cathode regions among the plurality of cathode regions,    wherein one of the plurality of cathode regions is electrically connected to the gate electrode of the field-effect transistor, and    wherein the other one of the plurality of cathode regions is electrically connected to the source region of the field-effect transistor.    
   
   
       3 . The semiconductor device according to  claim 1 , 
 wherein the gate electrode, and the first and second conductive films are made of polycrystalline silicon films, and    wherein the resistance of the gate electrode is lower than that of the first conductive film.    
   
   
       4 . The semiconductor device according to  claim 1 , wherein the gate electrode and the first conductive film are electrically connected to each other.  
   
   
       5 . The semiconductor device according to  claim 1 , wherein the thickness of the first insulating film is larger than that of the gate insulating film.  
   
   
       6 . A semiconductor device comprising: 
 (a) a field-effect transistor having a trench gate structure with a dummy gate electrode; and    (b) a protective diode,    wherein the field-effect transistor and the protective diode are formed over the same semiconductor substrate.    
   
   
       7 . The semiconductor device according to  claim 6 , wherein a cathode region of the protective diode is connected to the gate electrode of the field-effect transistor, and an anode region of the protective diode is connected to a source region of the field-effect transistor.  
   
   
       8 . The semiconductor device according to  claim 6 , wherein the anode region of the protective diode is connected to the gate electrode of the field-effect transistor, and the cathode region of the protective diode is connected to the source region of the field-effect transistor.  
   
   
       9 . The semiconductor device according to  claim 6 , wherein a plurality of protective diodes are connected between the gate electrode and the source region of the field-effect transistor.  
   
   
       10 . The semiconductor device according to  claim 9 , wherein one cathode region of the plurality of protective diodes whose anode regions are connected to each other is connected to the gate electrode of the field-effect transistor, and the other cathode region thereof is connected to the source region of the field-effect transistor.  
   
   
       11 . The semiconductor device according to  claim 6 , wherein a polycrystalline silicon film for the protective diode included in the protective diode is formed in the same step as that of a polycrystalline silicon film for the dummy gate electrode included in the dummy gate electrode.  
   
   
       12 . The semiconductor device according to  claim 6 , wherein a cathode region of the protective diode is formed in the same step as that of the source region of the field-effect transistor.  
   
   
       13 . The semiconductor device according to  claim 6 , wherein a concentration of impurities introduced in the dummy gate electrode is lower than that of impurities introduced in the gate electrode of the field-effect transistor.  
   
   
       14 . The semiconductor device according to  claim 6 , wherein a resistance of the dummy gate electrode is larger than that of the gate electrode of the field-effect transistor.  
   
   
       15 . The semiconductor device according to  claim 6 , wherein a thickness of a lead-out part for the dummy gate electrode is smaller than that of a lead-out part for the gate electrode of the field-effect transistor.  
   
   
       16 . The semiconductor device according to  claim 6 , wherein the dummy gate electrode and the gate electrode of the field-effect transistor are electrically connected to each other.  
   
   
       17 . The semiconductor device according to  claim 6 , wherein a first contact hole connected to the dummy gate electrode and a second contact hole connected to the gate electrode of the field-effect transistor are arranged linearly, and a gate interconnection is disposed linearly over the first contact hole and the second contact hole.  
   
   
       18 . The semiconductor device according to  claim 6 , 
 wherein the dummy gate electrode is connected to the source region of the field-effect transistor, and    wherein the first contact hole connected to the dummy gate electrode and the second contact hole connected to the gate electrode of the field-effect transistor are arranged linearly, and in a position where a source electrode over the first contact hole is formed in a recessed shape, the corresponding gate interconnection over the second contact hole is formed in a convex shape, while, in a position where the source electrode is formed in a convex shape, the corresponding gate interconnection is formed in a recessed shape.    
   
   
       19 . A method of manufacturing a semiconductor device, the semiconductor device including: a field-effect transistor having a trench gate structure with a dummy gate electrode; and a protective diode, 
 the method comprising a step of:    forming a polycrystalline silicon film for the protective diode, which is included in the protective diode, and a polycrystalline silicon film for the dummy gate electrode, which is included in the dummy gate electrode, in the same step.    
   
   
       20 . The method according to  claim 19 , further comprising a step of: 
 forming the cathode region of the protective diode and the source region of the field-effect transistor in the same step.    
   
   
       21 . A method of manufacturing a semiconductor device, the method comprising the steps of: 
 (a) forming a trench in a semiconductor substrate;    (b) forming an insulating film over the semiconductor substrate including an inner surface of the trench;    (c) forming a first polycrystalline silicon film over the insulating film;    (d) introducing an impurity into the first polycrystalline silicon film;    (e) annealing the first polycrystalline silicon film with the impurity introduced therein;    (f) forming, by patterning the first polycrystalline silicon film, a dummy gate electrode with a part of the first polycrystalline silicon film left in the trench, while forming an anode region of the protective diode over the semiconductor substrate;    (g) forming a gate insulating film over the semiconductor substrate including the trench;    (h) forming a second polycrystalline silicon film with a conductive impurity introduced therein over the gate insulating film;    (i) forming a gate electrode with a part of the second polycrystalline silicon film left in the trench by patterning the second polycrystalline silicon film;    (j) forming a semiconductor region for channel formation by introducing an impurity into a predetermined region of the semiconductor substrate;    (k) forming a source region by introducing an impurity into a predetermined region of the semiconductor substrate; and    (l) forming a cathode region of the protective diode by introducing an impurity into a predetermined region of the semiconductor substrate.    
   
   
       22 . The method according to  claim 21 , wherein the step (k) and the step (l) are carried out in the same step.  
   
   
       23 . The method according to  claim 21 , wherein the step (e) is carried out before the step (j).  
   
   
       24 . The method according to  claim 21 , wherein a concentration of the impurities introduced into the first polycrystalline silicon film is lower than that of the impurities introduced into the second polycrystalline silicon film.  
   
   
       25 . The method according to  claim 21 , wherein, in the step (d), the impurity is introduced by an ion implantation method after forming the first polycrystalline silicon film, and wherein, in the step (h), the second polycrystalline silicon film previously containing the impurity is deposited.  
   
   
       26 . The method according to  claim 21 , wherein a thickness of a lead-out part for the dummy gate electrode is smaller than that of a lead-out part for the gate electrode.