US2006268607A1PendingUtilityA1

Operation method of non-volatile memory structure

46
Assignee: SKYMEDI CORPPriority: Feb 28, 2005Filed: Jul 24, 2006Published: Nov 30, 2006
Est. expiryFeb 28, 2025(expired)· nominal 20-yr term from priority
Inventors:Fuja Shone
H10D 30/6892H10D 30/687G11C 16/0458G11C 16/0491H10B 69/00H10B 41/30
46
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An operation method for a memory structure formed between two doping regions serving as bit lines in a semiconductor substrate, the memory structure comprising a first conductive line serving as a select gate and being formed above the semiconductor substrate, two conductive blocks serving as floating gates and being formed at the two sides of the first conductive line and insulated from the first conductive line with two first dielectric spacers therebetween, a first dielectric layer formed on the two second conductive blocks, a selected second conductive line serving as a word line and being formed on the first dielectric layer and substantially perpendicular to the two doping regions, and a plurality of unselected second conductive lines parallel to the selected second conductive line; wherein reading the programmed status of one of the conductive blocks comprising the step of putting a bias voltage on the doping region next to the other conductive block so that the depletion region is created across the other conductive block whereby ignoring the effect of the other conductive block if being programmed, and the unselected second conductive lines are applied by negative voltages.

Claims

exact text as granted — not AI-modified
1 . An operation method for a non-volatile memory structure formed between two doping regions serving as bit lines in a semiconductor substrate, the non-volatile memory structure comprising a first conductive line serving as a select gate and being formed above the semiconductor substrate, two conductive blocks serving as floating gates and being formed at the two sides of the first conductive line and insulated from the first conductive line with two first dielectric spacers therebetween, a first dielectric layer formed on the two second conductive blocks, a selected second conductive line serving as a word line and being formed on the first dielectric layer and substantially perpendicular to the two doping regions, and a plurality of unselected second conductive lines parallel to the selected second conductive line; 
 wherein reading the programmed status of one of the conductive blocks comprising the step of putting a bias voltage on the doping region next to the other conductive block so that the depletion region is created across the other conductive block whereby ignoring the effect of the other conductive block if being programmed, and the unselected second conductive lines are applied by negative voltages.    
   
   
       2 . The operation method of  claim 1 , wherein the conductive block is programmed by generating a bias voltage underneath the conductive block, and the bias voltage is generated by turning on the first conductive line and the two conductive blocks and applying different voltages to the two doping regions.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.