Digital image processor for a digital camera

Abstract

A digital image process for a digital camera contains a preprocessor and a postprocessor. The preprocessor can include, for example, a uniformity corrector, a sampling filter, a modulation transformer, and a ditherer. The postprocessor can include a color interpolator, an RGB reconstruction block, a digital compressor, and a color pattern data buffer. The digital image process is programmable to operate one or more of the processing blocks of one or both the preprocessor and the postprocessor for flexible programming that can adapt to the requirements of various digital camera designs or users.

1 . A digital image processor for use in a digital camera having an image capture unit arranged lo output analog signals that represent the captured image, a converter unit for converting analog representations of the captured image to digital representations of the image, a memory for storing digital representations of the image, and a processing unit capable of directing components included in the digital camera, the digital image processor comprising: 
 an input data stream processor for pre-processing images received from the converter unit and storing the pre-processed images in the memory; and    an output data stream processor arranged to receive pre-processed images and post-process the retrieved images into a viewable form.    
   
   
       2 . A digital image processor as recited in  claim 1  further comprising a system bus within the digital image processor, wherein the input data stream processor, the output data stream processor and the memory are coupled to the system bus.  
   
   
       3 . A digital image processor as recited in  claim 2 , wherein the output data stream processor includes a color interpolator arranged to derive an unknown pixel color value associated with a first pixel based upon at least one known pixel color value associated with at least one other pixel using pixel color weight factors associated with the image sensor.  
   
   
       4 . A digital image processor as recited in  claim 3  further including a color pattern setting buffer connected to the color interpolator capable of storing image sensor data associated with the image sensor included in the image capture unit, the image sensor data being used to derive the associated pixel color weight factors.  
   
   
       5 . A digital image processor for use in a digital camera as recited in  claim 3 , wherein the output data stream processor further includes an RGB reconstructor connected to the color interpolator capable of converting the digital image to an RGB format as needed.  
   
   
       6 . A digital image processor for use in a digital camera as recited in  claim 5 , wherein the output data stream processor further includes a digital image compressor connected to the color interpolator and the RGB reconstructor capable of appropriately compressing digital image files.  
   
   
       7 . A digital image processor as recited in  claim 6  wherein the color interpolator, the RGB reconstructor, and the compressor are each connected to the system bus.  
   
   
       8 . A digital image processor as recited in  claim 1 , wherein the input data stream processor does not include any color interpolation.  
   
   
       9 . A digital image processor as recited in  claim 2 , further comprising a programmable universal controller arranged to generate operational signals useful in the operation of components included in the digital camera.  
   
   
       10 . A digital image processor as recited in  claim 9 , wherein the programmable universal controller includes an image sensor controller for generating signals useful for synchronizing the image sensor.  
   
   
       11 . A digital image processor as recited in  claim 10 , wherein the image sensor controller includes a programmable clock generator that may be programmed to generate both symmetric clock signals and non-symmetric clock signals.  
   
   
       12 . A digital image processor as recited in  claim 11 , wherein the programmable clock generator is arranged to receive a fast clock signal and includes a programmable logic block having a programmable clock register, wherein the programmable clock register may be programmed using data stored in the programmable logic block to create a desired symmetric or non-symmetric clock signal based at least in part upon the fast clock signal.  
   
   
       13 . A digital image processor as recited in  claim 11 , wherein the programmable clock generator includes a counter buffer arranged to receive a fast clock signal, the counter buffer being connected to a memory unit, wherein the memory unit includes programmable data registers capable of storing clock signal characterizing data used by the counter buffer to create a desired symmetric clock signal or a desired non-symmetric clock signal based at least in part upon the fast clock signal.  
   
   
       14 . A digital image processor as recited in  claim 13 , wherein the clock signal characterizing data includes a clock tick value and an associated clock signal output value.  
   
   
       15 . A digital image processor as recited in  claim 10 , wherein the programmable universal controller further includes a programmable analog reference signal generator for generating analog reference signals useful in the operation of analog components included in the digital camera.  
   
   
       16 . A digital image processor as recited in  claim 15 , wherein the programmable analog reference signal generator includes: 
 a programmable register for storing analog reference signal characterizing data; and    a pulse width modulation (PWM) block that uses the analog reference signal characterizing data stored in the programmable register and the fast clock signal to create the desired analog reference signal.    
   
   
       17 . A digital image processor recited in  claim 2 , wherein the input data stream processor includes a non-uniformity corrector capable of correcting non-uniformities included in the digital representations of the image received from the converter unit.  
   
   
       18 . A digital image processor recited in  claim 17 , wherein the input data stream processor further includes: 
 a programmable sampling filter connected to the non-uniformity corrector being capable of systematically selecting portions of the corrected digital image received from the non-uniformity corrector;    a modular transformer connected to the programmable sampling filter being capable of at least correcting aberrations in the sampled digital image received from the programmable sampling filter; and    a ditherer connected to the modular transformer being capable of at least correcting any aliasing in the digital image received from the modular transformer.    
   
   
       19 . A digital image processor recited in  claim 18 , wherein the digital image processor further includes an authenticity stamping unit connected to the non-uniformity corrector and the system bus.  
   
   
       20 . A digital image processor recited in  claim 19 , wherein the authenticity stamping unit includes an authenticity stamper connected to a secure key buffer for storing a secure key, the authenticity stamper being capable of encryptically combining digital camera identification and the secure key with an associated non-uniformity corrected digital image.  
   
   
       21 . A digital image processor as recited in  claim 20 , further comprising: 
 a memory interface controller connected to the system bus, the memory interface controller being capable of providing control signals suitable for controlling the storing of image data in and the retrieving image data From the memory;    a central processing unit (CPU) interface operatively connected to the system bus for managing communications between the digital image processor and a digital camera system CPU; and    system clock connected to the system bus, the system clock being capable of providing clock signals.    
   
   
       22 . A digital image processor as recited in  claim 21 , wherein the non-uniformity corrector sends a first corrected digital image directly to the programmable sampling filter which, in turn, sends the sampled digital image to the system bus, the sampled digital image being capable of display on a viewer in a cineview mode, the cineview mode being capable of providing the digital camera with “through the lens viewing”.  
   
   
       23 . A digital image processor as recited in  claim 22 , wherein the non-uniformity corrector outputs an associated second corrected digital image to the system bus, the second digital image, in turn, being capable of storage in the memory in a capture mode.  
   
   
       24 . A digital image processor as recited in  claim 23 , wherein the digital camera further includes an input/output (I/O) block suitable for coupling the microprocessor to external devices.  
   
   
       25 . A digital image processor as recited in  claim 2 , wherein the output data stream processor is arranged such that its operation does not interfere with the operation of the input data stream processor or taking pictures using the digital camera.  
   
   
       26 . A digital camera comprising: 
 an image capture unit capable arranged to output analog signals that represent a captured image;    a converter unit for converting analog representations of the captured image to digital representations of the image in the form of pixels;    a digital image processor for use in a digital camera as recited in  claim 1;  and memory for storing the digital representations of the image.