Semiconductor memory device with redundancy function

Abstract

A fuse and fuse latch includes first and second fuse and fuse latches each serving as a redundancy information storage circuit. Fuse elements and a fuse latch are provided in each of the first and second fuse and fuse latches. The first and second fuse and fuse latches each output latched data as serial data to a fuse data transfer control circuit. The fuse data transfer control circuit serving as a redundancy information creation circuit is configured of a counter and a data transfer control circuit. The data transfer control circuit combines data output from the first and second fuse and fuse latches, thereby to create new data.

1 . A semiconductor memory device comprising: 
 a plurality of redundancy information storage circuits each including a plurality of nonvolatile storage elements which store redundancy information used to replace a defective cell existing in a memory cell array by a spare cell in a spare memory cell array; and    a redundancy information creation circuit which receives a plurality of redundancy information stored in the plurality of redundancy information storage circuits, combines the plurality of redundancy information, and thereby creates new redundancy information.    
   
   
       2 . The semiconductor memory device according to  claim 1 , wherein of the plurality of redundancy information stored in the plurality of redundancy information storage circuits, redundancy information stored in at least one redundancy information storage circuit is data-compressed.  
   
   
       3 . The semiconductor memory device according to  claim 1 , wherein the plurality of redundancy information stored in the plurality of redundancy information storage circuits are all data-compressed.  
   
   
       4 . The semiconductor memory device according to  claim 1 , wherein the plurality of redundancy information storage circuits includes a redundancy information storage circuit different in information storage capacity.  
   
   
       5 . The semiconductor memory device according to  claim 1 , wherein the redundancy information creation circuit cancels creation of the new redundancy information in accordance with redundancy information stored in the plurality of redundancy information storage circuits.  
   
   
       6 . The semiconductor memory device according to  claim 1 , wherein the plurality of nonvolatile storage elements includes a plurality of types of nonvolatile storage elements different in programming scheme.  
   
   
       7 . The semiconductor memory device according to  claim 6 , wherein at least one of the plurality of types of the nonvolatile storage elements is programmed by a scheme of irradiating laser light.  
   
   
       8 . The semiconductor memory device according to  claim 6 , wherein at least one of the plurality of types of the nonvolatile storage elements is programmed by an electrical scheme.  
   
   
       9 . The semiconductor memory device according to  claim 1 , wherein the redundancy information creation circuit expands a plurality of redundancy information stored in the plurality of redundancy information storage circuits and acquires logical sums of the plurality of redundancy information expanded, thereby to combine the redundancy information and create the new redundancy information.  
   
   
       10 . The semiconductor memory device according to  claim 9 , wherein an expansion scheme for expanding the plurality of redundancy information includes at least two expansion schemes.  
   
   
       11 . The semiconductor memory device according to  claim 10 , wherein at least one expansion scheme of the at least two expansion schemes is an expansion scheme which expands a compressed bit pattern to a fixed-length bit pattern.  
   
   
       12 . The semiconductor memory device according to  claim 11 , wherein the expansion scheme to expand to the fixed-length bit pattern expands the compressed bit pattern to one of a first bit-length bit pattern or a second bit-length bit pattern.  
   
   
       13 . The semiconductor memory device according to  claim 10 , wherein one expansion scheme of the at least two expansion schemes is configured of address bits and data bits, the contents of the data bits is written in an area in which is designated by the address bits.  
   
   
       14 . The semiconductor memory device according to  claim 10 , wherein one expansion scheme of the at least two expansion schemes outputs redundancy information without being modified.  
   
   
       15 . A semiconductor memory device comprising: 
 a memory cell array having a plurality of memory cells;    a spare memory cell array having a plurality of spare cells used to compensate for a defective cell existing in the memory cell array;    a plurality of redundancy information storage circuits each including a plurality of nonvolatile storage elements which store redundancy information used to replace a defective cell existing in the memory cell array by a spare cell in the spare memory cell array;    a redundancy information creation circuit which receives a plurality of redundancy information stored in the plurality of redundancy information storage circuits, combines the plurality of redundancy information, and thereby creates new redundancy information; and    a selection circuit which receives redundancy information created in the redundancy information creation circuit and selection information for a memory cell existing in the memory cell array, and selects any one of a memory cell existing in the memory cell array and a spare cell existing in the spare memory cell array in accordance with the information received.    
   
   
       16 . The semiconductor memory device according to  claim 15 , wherein of the plurality of redundancy information stored in the plurality of redundancy information storage circuits, redundancy information stored in at least one redundancy information storage circuit is data-compressed.  
   
   
       17 . The semiconductor memory device according to  claim 15 , wherein the plurality of redundancy information stored in the plurality of redundancy information storage circuits are all data-compressed.  
   
   
       18 . The semiconductor memory device according to  claim 15 , wherein the plurality of redundancy information storage circuits includes a redundancy information storage circuit different in information storage capacity.  
   
   
       19 . The semiconductor memory device according to  claim 15 , wherein the redundancy information creation circuit cancels creation of the new redundancy information in accordance with redundancy information stored in the plurality of redundancy information storage circuits.  
   
   
       20 . The semiconductor memory device according to  claim 15 , wherein the plurality of nonvolatile storage elements includes a plurality of types of nonvolatile storage elements different in programming scheme.