Method for seamlessly changing power modes in an ADSL system

Abstract

A DMT system and method with the capability to adapt the system bit rate on-line in a seamless manner. The DMT system provides a robust and fast protocol for completing this seamless rate adaptation. The DMT system also provides a framing and encoding method with reduced overhead compared to conventional DMT systems. The DMT system and method provide seamless rate adaptation with the provision of different power levels. This framing and encoding method enables a system with seamless rate adaptation capability. The system and method of the invention can be implemented in hardware, or alternatively in a combination of hardware and software

1 . In a multicarrier transmission system including a transmitter and a receiver, the transmitter and receiver using a first bit allocation table to transmit a plurality of codewords at a first transmission bit rate in a first power mode, the plurality of code words having a specified codeword size and including a specified number of parity bits for forward error correction, and a specified interleaving parameter for interleaving the plurality of codewords, the system seamlessly entering a second power mode comprising: 
 means for storing a second bit allocation table at the receiver and at the transmitter for transmitting codewords at a second transmission bit rate in the second power mode;    means for synchronizing use of the second bit allocation table between the transmitter and receiver; and    means for transitioning the second power mode by using the second bit allocation table to transmit codewords, wherein the specified interleaving parameter, the specified codeword size, and the specified number of parity bits for forward error correction used to transmit codewords in the first power mode are also used to transmit codewords in the second power mode to achieve a seamless change in power mode.    
     
     
         2 . The system of  claim 1 , wherein the synchronizing includes sending a flag signal.  
     
     
         3 . The system of  claim 2 , wherein the flag signal is a predefined signal.  
     
     
         4 . The system of  claim 3 , wherein the predefined signal is a sync symbol with a predefined phase shift.  
     
     
         5 . The system of  claim 3 , wherein the predefined signal is an inverted sync symbol.  
     
     
         6 . The system of  claim 2 , wherein the transmitter transmits the flag signal to the receiver.  
     
     
         7 . The system of  claim 2 , wherein the receiver transmits the flag signal to the transmitter.  
     
     
         8 . The system of  claim 1 , wherein the second power mode is a low power mode.  
     
     
         9 . The system of  claim 8 , further comprising means for allocating zero bits to carrier signals to achieve a transmission bit rate of approximately zero kilobits per second in the low power mode.  
     
     
         10 . The system of  claim 8 , further comprising means for transmitting a pilot tone for timing recovery when operating in the low power mode.  
     
     
         11 . The system of  claim 8 , further comprising means for periodically transmitting a sync symbol when operating in the low power mode.  
     
     
         12 . The system of  claim 2 , further comprising means for using the first bit allocation table for transmitting a plurality of DMT symbols in the first power mode and switching to the second bit allocation table for transmitting the plurality of the DMT symbols in the second power mode, wherein the second bit allocation table is used for transmission starting with a predetermined one of the DMT symbols that follows the transmission of the flag signal.  
     
     
         13 . The system of  claim 12 , wherein the predetermined DMT symbol is the first DMT symbol that follows the transmission of the flag signal.  
     
     
         14 . The system of  claim 1 , wherein the second power mode is a full power mode.  
     
     
         15 . The system of  claim 1 , wherein the first power mode is a full power mode, and the second power mode is a low power mode.  
     
     
         16 . The system of  claim 1 , wherein the first power mode is a low power mode, and the second power mode is a full power mode.