Three-dimensional integrated circuit structure and method of making same

Abstract

Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures. Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate. The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors. Ferroelectric memory devices, Ferromagnetic memory devices, chalcogenide phase change devices, may be formed in a stackable add-on layer for use in conjunction with a separately fabricated substrate. Stackable add-on layers may include interconnect lines.

1 - 20 . (canceled)  
     
     
         21 . A method, comprising: 
 forming a detach layer below a surface of a first substrate; and    forming at least one pn junction between the detach layer and surface of the first substrate.    
     
     
         22 . The method of  claim 21 , wherein the pn junction includes single crystal semiconductor material.  
     
     
         23 . The method of  claim 21 , further including forming a conductive layer on the surface of the first substrate.  
     
     
         24 . The method of  claim 23 , further including providing an inter-layer dielectric layer with a second conductive layer on its surface.  
     
     
         25 . The method of  claim 24 , further including bonding the first and second conductive layers together.  
     
     
         26 . The method of  claim 25 , further including removing a portion of the first substrate between the detach layer and an opposed surface of the first substrate.  
     
     
         27 . The method of  claim 21 , wherein the detach layer includes an oxide or porous semiconductor region.  
     
     
         28 . The method of  claim 21 , wherein the pn junction is formed between blanket layers of oppositely doped semiconductors.  
     
     
         29 . A method, comprising: 
 providing a first substrate having a detach layer below its surface and a first plurality of differently doped semiconductor layers between the detach layer and surface of the first substrate;    providing a second substrate which carries an inter-layer dielectric layer having a via and interconnection line; and    bonding the inter-layer dielectric layer to the first substrate.    
     
     
         30 . The method of  claim 29 , further including providing a first conductive layer on the substrate so that the inter-layer dielectric layer and first substrate are bonded through the first conductive line.  
     
     
         31 . The method of  claim 29 , further including removing a portion of the first substrate so that the first plurality of differently doped semiconductor layers are carried by the second substrate.  
     
     
         32 . The method of  claim 31 , further including providing a second conductive layer on an exposed surface of the first plurality of differently doped semiconductor layers.  
     
     
         33 . The method of  claim 32 , further including providing a third substrate having a detach layer below its surface and a second plurality of differently doped semiconductor layers between the detach layer and surface of the third substrate.  
     
     
         34 . The method of  claim 33 , wherein the first and second plurality of differently doped semiconductor layers are blanket layers.  
     
     
         35 . The method of  claim 33 , further including providing a third conductive layer on the surface of the third substrate.  
     
     
         36 . The method of  claim 35 , further including bonding the third substrate to the first plurality of differently doped semiconductor layers through the second and third conductive layers.  
     
     
         37 . The method of  claim 36 , further including removing a portion of the third substrate so that the second plurality of differently doped semiconductor layers is carried by the second substrate.  
     
     
         38 . The method of  claim 37 , wherein the first and second plurality of differently doped semiconductor layers include single crystal semiconductor material.  
     
     
         39 . The method of  claim 29 , wherein the detach layer is formed by implanting hydrogen.  
     
     
         40 . A method, comprising: 
 providing a substrate which carries a first inter-layer dielectric layer;    providing a first stackable add-on layer;    bonding the first stackable add-on layer to the first inter-layer dielectric layer; and    processing the first stackable add-on layer to form a first vertically oriented semiconductor device.    
     
     
         41 . The method of  claim 40 , wherein the first stackable add-on layer includes single crystalline semiconductor material.  
     
     
         42 . The method of  claim 40 , wherein the first vertically oriented semiconductor device includes a stack of differently doped semiconductor layers.  
     
     
         43 . The method of  claim 42 , further including forming a gate dielectric around the stack of differently doped semiconductor layers, and forming a gate electrode around the gate dielectric.  
     
     
         44 . The method of  claim 43 , wherein the gate dielectric is formed at a temperature below about 650° C.  
     
     
         45 . The method of  claim 43 , wherein the gate electrode includes a metal.  
     
     
         46 . The method of  claim 43 , wherein the stack of differently doped semiconductor layers, gate dielectric, and gate electrode operate as a memory device.  
     
     
         47 . The method of  claim 43 , wherein the gate dielectric includes an oxide-nitride-oxide layer stack of materials.