Thin film transistor array panel and method of manufacturing the same

Abstract

A thin film transistor (“TFT”) array panel is provided. The TFT array panel includes an insulation substrate, a gate line formed on the insulation substrate and including a gate electrode, a data line insulated from and intersecting the gate line, and including a source electrode, a drain electrode opposite to the source electrode on the gate line, and a semiconductor formed in a layer between the data line and the gate line, and having a protruding portion extending below the drain electrode, wherein a portion of the semiconductor extending towards the drain electrode, from an area occupied by the data line, is positioned within an occupying area of the gate line including the gate electrode.

1 . A thin film transistor array panel comprising: 
 an insulation substrate;    a gate line formed on the insulation substrate and including a gate electrode;    a data line insulated from and intersecting the gate line, and including a source electrode;    a drain electrode disposed opposite to the source electrode on the gate line; and    a semiconductor formed in a layer between the data line and the gate line, the semiconductor having a protruding portion extending below the drain electrode,    wherein a portion of the semiconductor extending towards the drain electrode, from an area occupied by the data line, is disposed within an occupying area of the gate line including the gate electrode.    
   
   
       2 . The thin film transistor array panel of  claim 1 , wherein the drain electrode is positioned within an occupying area of the semiconductor.  
   
   
       3 . The thin film transistor array panel of  claim 1 , wherein the protruding portion of the semiconductor is positioned within the occupying area of the gate line including the gate electrode.  
   
   
       4 . The thin film transistor array panel of  claim 1 , further comprising a pixel electrode connected to the drain electrode.  
   
   
       5 . The thin film transistor array panel of  claim 4 , wherein the pixel electrode has a branch portion extended toward the drain electrode and the branch portion is connected to the drain electrode.  
   
   
       6 . The thin film transistor array panel of  claim 5 , wherein only the branch portion of the pixel electrode overlaps with the gate line.  
   
   
       7 . The thin film transistor array panel of  claim 4 , wherein the pixel electrode contacts an upper surface and a side surface of the drain electrode.  
   
   
       8 . The thin film transistor array panel of  claim 7 , wherein the pixel electrode contacts the semiconductor.  
   
   
       9 . The thin film transistor array panel of  claim 1 , wherein a combined outer periphery of the drain electrode, source electrode, and a channel portion between the drain electrode and source electrode matches an outer periphery of the protruding portion of the semiconductor.  
   
   
       10 . The thin film transistor array panel of  claim 1 , wherein the protruding portion of the semiconductor is blocked from light penetrating the insulation substrate by the gate line including the gate electrode.  
   
   
       11 . A thin film transistor array panel comprising: 
 an insulation substrate;    a gate line formed on the insulation substrate and including a gate electrode;    a gate insulating layer formed on the gate line;    a semiconductor stripe formed on the gate insulating layer, the semiconductor stripe having a protruding portion;    a data line formed on the semiconductor stripe and intersecting the gate line, the data line including a source electrode;    a drain electrode formed on the protruding portion of the semiconductor stripe;    a passivation layer formed on the data line and the drain electrode and having a contact hole exposing the drain electrode; and    a pixel electrode formed on the passivation layer and connecting to the drain electrode through the contact hole,    wherein a portion of the semiconductor stripe extending toward the drain electrode, from an area occupied by the data line, is disposed within an occupying area of the gate line including the gate electrode.    
   
   
       12 . The thin film transistor array panel of  claim 11 , wherein the drain electrode is positioned within an occupying area of the semiconductor stripe.  
   
   
       13 . The thin film transistor array panel of  claim 11 , wherein the protruding portion of the semiconductor stripe is positioned within an occupying area of the gate line including the gate electrode.  
   
   
       14 . The thin film transistor array panel of  claim 11 , wherein the pixel electrode has a branch portion extended toward the drain electrode and the branch portion is connected to the drain electrode.  
   
   
       15 . The thin film transistor array panel of  claim 14 , wherein only the branch portion of the pixel electrode overlaps with the gate line.  
   
   
       16 . The thin film transistor array panel of  claim 11 , wherein the contact hole exposes the drain electrode and portions of the semiconductor stripe around the drain electrode.  
   
   
       17 . The thin film transistor array panel of  claim 16 , wherein the pixel electrode contacts an upper surface and a side surface of the drain electrode exposed through the contact hole.  
   
   
       18 . The thin film transistor array panel of  claim 17 , wherein the pixel electrode comes in contact with the portions of the semiconductor stripe that are exposed through the contact hole.  
   
   
       19 . The thin film transistor array panel of  claim 18 , wherein the pixel electrode has a branch portion and the branch portion is connected to the drain electrode and the semiconductor.  
   
   
       20 . The thin film transistor array panel of  claim 19 , wherein only some of the portions of the semiconductor stripe exposed through the contact hole are covered with the pixel electrode.  
   
   
       21 . The thin film transistor array panel of  claim 9 , wherein a combined outer periphery of the drain electrode, source electrode, and a channel portion between the drain electrode and source electrode matches an outer periphery of the protruding portion of the semiconductor stripe.  
   
   
       22 . The thin film transistor array panel of  claim 9 , wherein the protruding portion of the semiconductor stripe is blocked from light penetrating the insulation substrate by the gate line including the gate electrode.  
   
   
       23 . A method of manufacturing a thin film transistor array panel, the method including: 
 forming a gate line and a gate electrode on an insulation substrate;    forming a semiconductor layer and a data metal layer on the gate line and gate electrode on the insulation substrate; and,    forming a semiconductor stripe and a protruding portion from the semiconductor layer and a data line, source electrode, and drain electrode from the data metal layer using one mask,    wherein forming the semiconductor stripe and protruding portion includes forming the protruding portion within an area occupied by the gate line and gate electrode.    
   
   
       24 . The method of  claim 23 , further comprising forming an ohmic contact layer between the semiconductor layer and the data metal layer, and forming an ohmic contact pattern from the ohmic contact layer using the one mask.