High resolution CMOS circuit using a marched impedance output transmission line

Abstract

Image sensor with CMOS output, an another circuit receiving input. The circuit operates like a transmission line, in current mode, with substantially zero voltage. The impedances are matched by setting bias currents.

1 - 17 . (canceled)  
   
   
       18 . A method of transmitting data from an image chip, the method comprising the steps of: 
 receiving at a receiving device image information from a first device having a first impedance; and    matching the first impedance to an input impedance of the receiving device by adjusting a bias current with a current source through at least one biased device in a way that renders the input impedance relatively independent of an input current.    
   
   
       19 . The method of  claim 18 , further comprising receiving a current bias, wherein a magnitude of the current bias sets the first impedance of the first device.  
   
   
       20 . The method of  claim 18 , wherein the image information receiving step comprises mirroring an input current in the first device.  
   
   
       21 . A system comprising: 
 a processor; and    a sensor communicating with the processor, the sensor comprising: 
 an image acquisition portion;  
 an image processing portion for receiving image information from the image acquisition portion, the image processing portion including CMOS circuitry with CMOS differential outputs having an output impedance;  
 an image receiving portion, having an input impedance for receiving the image information from the CMOS outputs, the image processing portion producing a current mode output and the image receiving portion receiving the current mode output;  
 an active impedance matching device, the active impedance matching device being adapted to match the output impedance of the image processing portion to the input impedance of the image receiving portion by adjusting a bias current with a current source through at least one biased device; and  
 a current mode driver having an output voltage swing of less than 0.5 volts.  
   
   
   
       22 . The system of  claim 21 , wherein the impedance matching portion comprises a first circuit on the image processing portion and a second circuit on the image receiving portion.  
   
   
       23 . The system of  claim 22 , wherein the first and second circuits include respective elements adapted to receive respective current biases, and wherein respective magnitudes of the current biases set the respective impedances.  
   
   
       24 . The system of  claim 21 , wherein the image receiving portion includes a current mirror part, that mirrors an input current.  
   
   
       25 . The system of  claim 21 , wherein the image acquisition portion is an active pixel sensor with a photosensor, an in-pixel buffer, and an in pixel select transistor.  
   
   
       26 . The system of  claim 22 , wherein the impedance matching device comprises a circuit on the image processing portion.  
   
   
       27 . The system of  claim 26 , wherein an output circuit of the image processing portion includes a transistor adapted to receive a current bias, wherein a magnitude of the current bias sets the output impedance of the image processing portion.  
   
   
       28 . The system of  claim 22 , wherein the impedance matching device comprises a circuit on the image receiving portion.  
   
   
       29 . The system of  claim 21 , wherein the impedance matching device adjusts the bias current in a way that renders the input impedance relatively independent of an input current.  
   
   
       30 . A system comprising: 
 a processor; and    an image sensor coupled to the processor, the image sensor comprising: 
 an image acquisition portion comprising an active pixel sensor with a photosensor, an in-pixel buffer, and an in pixel select transistor;  
 an image processing portion for receiving image information from the image acquisition portion, the image processing portion including a CMOS circuitry with CMOS differential outputs having an output impedance;  
 an image receiving portion, having an input impedance, for receiving the image information from the CMOS outputs, the image processing portion producing a current mode output and the image receiving portion receiving the current mode output; and  
 an active impedance matching device, the active impedance matching device being adapted to match the output impedance of the image processing portion to the input impedance of the image receiving portion,  
 wherein the image acquisition portion and the image processing portion operates at substantially zero voltage.  
   
   
   
       31 . A system comprising: 
 a processor; and    an image sensor coupled to the processor, the image sensor comprising: 
 an image acquisition portion;  
 an image processing portion having a current source, the image processing portion being adapted to receive image information from the image acquisition portion at a differential input; and  
 an impedance matching device having a current source, the impedance matching device being adapted to match an output impedance of the image acquisition portion to an input impedance of the image processing portion by adjusting bias current, from the current source, through the at least a pair of transistors in a way that renders the input impedance relatively independent of an input current.  
   
   
   
       32 . The system as in  claim 31 , wherein the image acquisition portion and the image processing portion each operate in a current mode.  
   
   
       33 . A system, the system comprising: 
 a processor; and    a sensor coupled to the processor, the sensor comprising: 
 an image acquisition portion;  
 an image processing portion, the image processing portion being adapted to receive image information from the image acquisition portion at a differential input; and  
 an impedance matching device, the impedance matching device being adapted to match an output impedance of the image acquisition portion to an input impedance of the image processing portion by adjusting bias current through at least one biased device in a way that renders the input impedance relatively independent of an input current;  
 wherein the image acquisition portion and the image processing portion each operate in a current mode, and the image acquisition portion and the image processing portion operate at substantially zero voltage.