MPEG video storage address generation apparatuses and methods for uniformly fetching and storing video data

Abstract

A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.

1 . A method for fetching and storing spatial data, temporal data, and combined data representing a plurality of digital MPEG video frames, the method comprising: 
 first storing the spatial data;    second storing the temporal data;    third storing the combined data, wherein the combined data comprises the spatial data and the temporal data;    first generating a first non-sequential and distinct digit pattern address sequence to be associated with the spatial data, as well as a first mapping from the spatial data to a distinct first address associated with the first non-sequential and distinct digit pattern address sequence and with a location for the first storing;    second generating a second non-sequential and distinct digit pattern address sequence to be associated with the temporal data, as well as a second mapping from the temporal data to a distinct second address associated with the second non-sequential and distinct digit pattern address sequence and with a location for the second storing; and    third generating a third non-sequential and distinct digit pattern address sequence to be associated with the combined data, as well as a third mapping from the combined data to a distinct third address associated with the third non-sequential and distinct digit pattern address sequence and with a location for the third storing;    wherein: 
 the first generating, the second generating, and the third generating are accomplished in part by following a unified scheme, which unified scheme comprises counting with n digits and swapping two or more of the n digits, wherein n is a positive integer.  
   
   
   
       2 . The method of  claim 1 , 
 wherein:    the first generating and the second generating are synonymous in the counting and the swapping of the unified scheme; and    the first generating and the second generating are distinct in the multiplexing of the unified scheme.    
   
   
       3 . The method of  claim 1 , 
 wherein:    the first storing further comprises storing the spatial data to an intracoded direct cosine transform (IDCT) buffer comprised in an intracoded direct cosine unit;    the second storing further comprises storing the temporal data to an MC buffer comprised in a motion compensation unit; and    the third storing further comprises storing the combined data to a DRAM buffer associated with a merge-and-store unit.    
   
   
       4 . The method of  claim 1 , 
 wherein:    each digit comprises a bit;    each non-sequential and distinct digit pattern address sequences comprises a non-sequential and distinct bit pattern address sequence;    the counting further comprises generating up to 2 n  number of distinct bit pattern address sequences;    the swapping further comprises swapping a pair of bits in each of 2 n  respectively associated distinct binary values comprising n bits, which swapping the pairs of bits generates up to n factorial number of non-sequential and distinct bit pattern address sequences from the 2 n  number of distinct bit pattern address sequences;    the unified scheme further comprises multiplexing in association with the counting, which multiplexing comprises selecting one or more of the n factorial number of non-sequential and distinct bit pattern address sequences to create one or more corresponding addressing schemes associated with the plurality of video frames;    the unified scheme is implemented in part by a unified hardware architecture comprising an n-bit counter for the counting, bit-swapping circuitry for the swapping, and a multiplexer for the multiplexing.    
   
   
       5 . The method of  claim 4 , wherein: 
 the first non-sequential and distinct digit pattern address sequence constitutes a first addressing scheme in accordance with the unified scheme;    the second non-sequential and distinct digit pattern address sequence constitutes a second addressing scheme in accordance with the unified scheme;    the third non-sequential and distinct digit pattern address sequence constitutes a third addressing scheme in accordance with the unified scheme;    the fetching and the storing of the spatial data use the first addressing scheme;    the fetching and the storing of the temporal data use the second addressing scheme; and    the fetching and the storing of the combined data use the third addressing scheme.    
   
   
       6 . The method of  claim 4 , wherein: 
 the counting comprised in the unified scheme and generating the up to 2 n  number of distinct bit pattern address sequences further comprises producing a first sequence of 2 n  number of sequential numbers, wherein each of the 2 n  sequential numbers is associated with one of the distinct binary values comprising n bits;    the pair of bits in each of the 2 n  distinct binary values associated with one of the up to 2 n  number of distinct bit pattern address sequences comprises an mth pair of bits, wherein m is an integer that ranges in value from 1 to (n!−1); and    the swapping of the pair of bits in each of the 2 n  distinct binary values further comprises swapping the mth pair of bits in each of the 2 n  distinct binary values to produce an (m+1)th sequence of 2 n  number of non-sequential numbers.    
   
   
       7 . The method of  claim 4 , wherein 
 the third generating is accomplished in part by twice following the swapping and the multiplexing of the unified scheme.    
   
   
       8 . A computer-readable medium carrying one or more sequences of instructions for fetching and storing spatial data, temporal data, and combined data representing compressed digital video, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform a method, the method comprising: 
 generating distinct address sequences to be associated with spatial data, temporal data, and combined data representing compressed digital video by counting up to 2 n  numbers, wherein n is a number of digits, and by swapping a pair of the n digits.    
   
   
       9 . The method of  claim 8 , wherein the compressed digital video comprises a plurality of digital MPEG video frames.  
   
   
       10 . The method of  claim 8 , wherein the generating distinct address sequences is further achieved by selecting for association respectively with each of the spatial data, the temporal data, and the combined data a distinct address sequence from the up to n factorial number of distinct address sequences obtained by the counting and the swapping.  
   
   
       11 . The method of  claim 10 , wherein the respective distinct address sequences associated with the spatial data, the temporal data, and the combined data are further associated with respective locations on computer-readable mediums for the fetching and the storing of the spatial data, the temporal data, and the combined data.  
   
   
       12 . The method of  claim 10 , wherein the counting, the swapping, and the selecting comprise a unified scheme by which the generating is accomplished in part.  
   
   
       13 . The method of  claim 12 , wherein the generating comprises: 
 first generating a first distinct address sequence to be associated with the spatial data, 
 as well as a first mapping from the spatial data to a location on a computer-readable medium associated with the storing and the fetching of the spatial data;  
   second generating a second distinct address sequence to be associated with the temporal data, 
 as well as a second mapping from the temporal data to a location on a computer-readable medium associated with the storing and the fetching of the temporal data; and  
   third generating a third distinct address sequence to be associated with the combined data, 
 as well as a third mapping for the combined data to a location on a computer-readable medium associated with the storing and the fetching of the combined data;  
   wherein the spatial data, the temporal data, and the combined data represent the compressed digital video, which compressed digital video comprises a plurality of digital MPEG video frames.    
   
   
       14 . An apparatus for fetching and storing spatial data, temporal data, and combined data representing a plurality of digital MPEG video frames, the apparatus comprising: 
 a first computer-readable medium for storing the spatial data;    a second computer-readable medium for storing the temporal data;    a third computer-readable medium for storing the combined data, wherein the combined data comprises the spatial data and the temporal data;    a first address generator for generating a first non-sequential and distinct bit pattern address sequence to be associated with the spatial data and for mapping the spatial data to a distinct first address associated with the first non-sequential and distinct pattern address sequence and with a first location, wherein the first location is associated with the first computer-readable medium, which first address generator comprises a first n-bit counter and a first bit-swapping circuit;    a second address generator for generating a second non-sequential and distinct bit pattern address sequence to be associated with the temporal data and for mapping the temporal data to a distinct second address associated with the second non-sequential and distinct bit pattern address sequence and with a second location, wherein the second location is associated with the second computer-readable medium, which second address generator comprises a second n-bit counter and a second bit-swapping circuit;    a third address generator for generating a third non-sequential and distinct bit pattern address sequence to be associated with the combined data and for mapping the combined data to a distinct third address associated with the third non-sequential and distinct bit pattern address sequence and with a third location, wherein the third location is associated with the third computer-readable medium, which third address generator comprises a third n-bit counter and a third bit-swapping circuit;    wherein: 
 the first address generator, the second address generator, and the third address generator are of a unified mechanism type, which unified mechanism type requires a unified hardware architecture comprising an n-bit counter and a bit-swapping circuit.  
   
   
   
       15 . The apparatus of  claim 14 , wherein: 
 the first computer-readable medium comprises an intracoded direct cosine unit comprising an IDCT buffer storing the spatial data;    the second computer-readable medium comprises a motion compensation unit comprising an MC buffer storing the temporal data; and    the third computer-readable medium comprises a merge-and-store unit associated with a DRAM buffer.    
   
   
       16 . The apparatus of  claim 14 , wherein: 
 the first address generator is merged with the second address generator;    the first n-bit counter and the second n-bit counter are synonymous; and    the first bit-swapping circuit and the second bit-swapping circuit are synonymous.    
   
   
       17 . The apparatus of  claim 14 , wherein: 
 the n-bit counter comprised in the unified hardware architecture generates up to 2 n  number of distinct bit pattern address sequences, wherein n is a positive integer;    the bit-swapping circuit comprised in the unified hardware architecture generates up to n factorial number of non-sequential and distinct bit pattern address sequences from the 2 n  number of distinct bit pattern address sequences by swapping a pair of bits in each of 2 n  respectively associated distinct binary values comprising n bits;    the unified hardware architecture further comprises a multiplexer corresponding to the n-bit counter comprised in the unified hardware architecture, wherein the multiplexer selects one or more of the n factorial number of non-sequential and distinct bit pattern address sequences to create one or more corresponding addressing schemes associated with the plurality of video frames;    the first n-bit counter, the second n-bit counter, and the third n-bit counter are structured and operated in accordance with the n-bit counter comprised in the unified hardware architecture;    the first bit-swapping circuit, the second bit-swapping circuit, and the third bit-swapping circuit are structured and operated in accordance with the bit-swapping circuit comprised in the unified hardware architecture; and    the first address generator, the second address generator, and the third address generator respectively and further comprise a first multiplexer, a second multiplexer, and a third multiplexer, which multiplexers are structured and operated in accordance with the unified hardware architecture.    
   
   
       18 . The apparatus of  claim 17 , wherein: 
 the n-bit counter comprised in the unified hardware architecture and generating the up to 2 n  number of distinct bit pattern address sequences further produces a first sequence of 2 n  number of sequential numbers, wherein each of the 2 n  sequential numbers is associated with one of the distinct binary values comprising n bits;    the pair of bits in each of the 2 n  distinct binary values associated with one of the up to 2 n  number of distinct bit pattern address sequences comprises an mth pair of bits, wherein m is an integer that ranges in value from 1 to (n!−1); and    the swapping of the pair of bits in each of the 2 n  distinct binary values further comprises swapping the mth pair of bits in each of the 2 n  distinct binary values to produce an (m+1)th sequence of 2 n  number of non-sequential numbers.    
   
   
       19 . The apparatus of  claim 17 , wherein: 
 the first non-sequential and distinct bit pattern address sequence constitutes a first addressing scheme in accordance with the unified hardware architecture;    the second non-sequential and distinct bit pattern address sequence constitutes a second addressing scheme in accordance with the unified hardware architecture;    the third non-sequential and distinct bit pattern address sequence constitutes a third addressing scheme in accordance with the unified hardware architecture;    the fetching and the storing of the spatial data uses the first addressing scheme;    the fetching and the storing of the temporal data uses the second addressing scheme; and    the fetching and the storing of the combined data uses the third addressing scheme.    
   
   
       20 . The apparatus of  claim 17 , wherein the third address generator further comprises: 
 a fourth bit-swapping circuit structured and operated in accordance with the unified hardware architecture; and    a fourth multiplexer structured and operated in accordance with the unified hardware architecture.