Digital transmitter

Abstract

An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

1 . A circuit comprising: 
 a semiconductor chip;    a transmitter circuit disposed on the chip, the transmitter circuit being operative to accept a digital input signal including a plurality of bits and send an output signal including a series of output current pulses, each bit of the digital input signal being represented by a single output current pulse, each output current pulse having a magnitude which is a function of the digital value of the bit represented by such output current pulse and of the digital values of one or more bits represented by one or more preceding output current pulses, the magnitude of each output current pulse being selected from plural possible magnitudes associated with the digital value of the bit represented by such output current pulse.    
     
     
         2 . The circuit as claimed in  claim 1  wherein output current pulses representing bits with digital values differing from the digital values of bits represented by a number of preceding output current pulses have greater magnitudes than output current pulses representing bits having digital values which are the same as the digital values of bits represented by the number of preceding output current pulses.  
     
     
         3 . The circuit as claimed in  claim 1  wherein each output current pulse has: 
 (i) a first magnitude when the bit represented by that output current pulse has a particular digital value and that particular digital value is the same as the digital value of a bit represented by an immediately preceding output current pulse; and    (ii) a second magnitude when the bit represented by that output current pulse has the particular digital value and that particular digital value is different from the digital value of a bit represented by an immediately preceding output current pulse;    the first magnitude being lower than the second magnitude.    
     
     
         4 . The circuit as claimed in  claim 1  wherein the transmitter circuit includes a plurality of current generators coupled to a common output.  
     
     
         5 . The circuit as claimed in  claim 4  wherein the transmitter circuit includes a circuit operative to select one or more of the current pulse generators and activate only the selected current pulse generators to provide each output current pulse.  
     
     
         6 . The circuit as claimed in  claim 4  wherein different ones of the plurality of current pulse generators are arranged to provide currents of different magnitudes.  
     
     
         7 . The circuit as claimed in  claim 4  wherein the common output includes a pair of output connections for connection to two conductors of a differential transmission line.  
     
     
         8 . The circuit as claimed in  claim 7  wherein each of the current pulse generators includes a current source, a first control element connected between one of the pair of output connections and the current source, a second control element being connected between the other one of the pair of output connections and the current source, each control element being operable to selectively block or permit flow of current.  
     
     
         9 . Data processing equipment comprising a circuit as claimed in  claim 7 , a differential transmission line coupled to the pair of output connections of the circuit, and a receiver circuit having a pair of input connections, the receiver circuit being operative to detect current pulses on the differential transmission line and convert the current pulses to digital values.  
     
     
         10 . Data processing equipment as claimed in  claim 9  further comprising a cabinet, wherein the circuit, the receiver circuit and the transmission line are disposed within the cabinet.  
     
     
         11 . Data processing equipment comprising a circuit as claimed in  claim 1 , a transmission line coupled to the transmitter circuit, and a receiver circuit coupled to the transmission line, the receiver circuit being operative to detect current pulses on the transmission line and convert the current pulses to digital values.  
     
     
         12 . Data processing equipment as claimed in  claim 11  further comprising a cabinet, wherein the circuit, the receiver circuit and the transmission line are disposed within the cabinet.  
     
     
         13 . The circuit as claimed in  claim 1  further comprising a memory, the transmitter circuit being coupled to the memory to accept the digital input signal from the memory.  
     
     
         14 . The circuit as claimed in  claim 1  further comprising a processor, the transmitter circuit being coupled to the processor to accept the digital input signal from the processor.  
     
     
         15 . The circuit as claimed in  claim 1  further comprising a peripheral device, the transmitter circuit being coupled to the peripheral device to accept the digital input signal from the peripheral device.  
     
     
         16 . Data processing equipment comprising a plurality of elements selected from the group consisting of processors, memories, and peripheral devices, at least one local signal path for conveying information between the elements, and at least one circuit as claimed in  claim 1 , the transmitter circuit being coupled to one of the elements for acceptance of the digital input signal from that one of the elements and being coupled to the local signal path for transmission of the current pulses along the local signal path to another one of the elements.  
     
     
         17 . Data processing equipment as claimed in  claim 16  wherein the transmitter circuit is operable to provide the current pulses with an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.  
     
     
         18 . A method of sending information comprising the steps of: 
 (a) accepting a digital input signal including a plurality of bits at a transmitter circuit within a semiconductor chip; and    (b) sending a series of output current pulses from the transmitter circuit, each bit of the digital input signal being represented by a single output current pulse, each output current pulse having a magnitude which is a function of the digital value of the bit represented by such output current pulse and of the digital values of one or more bits represented by one or more preceding output current pulses, the magnitude of each output current pulse being selected from plural possible magnitudes associated with the digital value of the bit represented by such output current pulse.    
     
     
         19 . The method as claimed in  claim 18  wherein output current pulses representing bits with digital values differing from the digital values of bits represented by a number of preceding output current pulses have greater magnitudes than output current pulses representing bits having digital values which are the same as the digital values of bits represented by the number of preceding output current pulses.  
     
     
         20 . The method as claimed in  claim 18  wherein each output current pulse has: 
 (i) a first magnitude when the bit represented by that output current pulse has a particular digital value and that particular digital value is the same as the digital value of a bit represented by an immediately preceding output current pulse; and    (ii) a second magnitude when the bit represented by that output current pulse has the particular digital value and that particular digital value is different from the digital value of a bit represented by an immediately preceding output current pulse;    the first magnitude being lower than the second magnitude.    
     
     
         21 . The method as claimed in  claim 18  wherein the step of sending the output current pulses includes actuating one or more of a plurality of current generators to send currents through a common output to form each output current pulse.  
     
     
         22 . The method as claimed in  claim 18  wherein the step of sending the output current pulses includes sending the pulses on a differential transmission line.  
     
     
         23 . The method as claimed in  claim 22  wherein the step of sending the pulses on the differential transmission line includes actuating one or more current sources and actuating control elements connected between the current sources and the transmission line to steer current passing through each of the one or more current sources to one conductor of the differential transmission line.  
     
     
         24 . The method as claimed in  claim 18  wherein the step of sending the output current pulses includes sending the output current pulses along a local signal path of a digital system.  
     
     
         25 . The method as claimed in  claim 24  wherein the steps of accepting the digital input signal and sending the output current pulses convey information between two or more elements of the digital system selected from the group consisting of processors, memories, and peripheral devices.  
     
     
         26 . The method as claimed in  claim 18  wherein the output current pulses constitute an output signal having a frequency of at least 1 GHz and a bandwidth greater than 100 MHz.  
     
     
         27 . A circuit comprising: 
 a semiconductor chip;    a transmitter circuit disposed on the chip, the transmitter circuit being operative to accept a digital input signal including a plurality of bits and send an output signal including a series of output bit signals, each such output bit signal representing one bit of the digital input signal, each output bit signal having a signal level which is a function of the digital value represented by such output bit signal and the digital values of the bits represented by one or more preceding output bit signals so that an output bit signal representing a bit having a digital value different from digital values of bits represented by the one or more preceding output bit signals will have a signal level of greater magnitude than an output bit signal representing a bit having the same digital value as the digital values of the bits represented by the one or more output bit signals, the transmitter circuit including an output connection, the transmitter circuit being operative to send the output bit signals in nonmodulated form through the-output connection, and the transmitter circuit being operable to provide the output signal with an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.    
     
     
         28 . The circuit as claimed in  claim 27  wherein the signal level of each output bit signal has: 
 (i) a first magnitude when the bit represented by that output bit signal has a particular digital value and that particular digital value is the same as the digital value of a bit represented by an immediately preceding output bit signal; and    (ii) a second magnitude when the bit represented by that output bit signal has the particular digital value and that particular digital value is different from the digital value of a bit represented by an immediately preceding output bit signal;    the first magnitude being lower than the second magnitude.    
     
     
         29 . Data processing equipment comprising a circuit as claimed in  claim 27 , a transmission line coupled to the transmitter circuit, and a receiver coupled to the transmission line, the transmitter circuit being operative to send the output bit signals in nonmodulated form on the transmission line.  
     
     
         30 . Data processing equipment as claimed in  claim 29  further comprising a cabinet, wherein the circuit, the receiver and the transmission line are disposed within the cabinet.  
     
     
         31 . The circuit as claimed in  claim 27  further comprising a memory, the transmitter circuit being coupled to the memory to accept the digital input signal from the memory.  
     
     
         32 . The circuit as claimed in  claim 27  further comprising a processor, the transmitter circuit being coupled to the processor to accept the digital input signal from the processor.  
     
     
         33 . The circuit as claimed in  claim 27  further comprising a peripheral device, the transmitter circuit being coupled to the peripheral device to accept the digital input signal from the peripheral device.  
     
     
         34 . Data processing equipment comprising a plurality of elements selected from the group consisting of processors, memories, and peripheral devices, at least one local signal path for conveying information between the elements, and at least one circuit as claimed in  claim 27 , the transmitter circuit being coupled to one of the elements to accept the digital input signal from such element and being coupled to the local signal path for transmission of the output signal along the local signal path to another one of the elements.  
     
     
         35 . A method of sending information comprising the steps of: 
 (a) accepting a digital input signal including a plurality of bits at a transmitter circuit within a semiconductor chip; and    (b) sending an output signal including a series of output bit signals in nonmodulated form from the transmitter circuit to a receiver circuit, each such output bit signal representing one bit of the digital input signal, each output bit signal having a signal level which is a function of the digital value of the bit represented by such output bit signal and of the digital values of the bits represented by one or more preceding output bit signals so that an output bit signal representing a bit having a digital value different from digital values of bits represented by the one or more preceding output bit signals will have a signal level of greater magnitude than an output bit signal representing a bit having the same digital value as the bits represented by the digital values of the one or more preceding output bit signals, the output signal having an output frequency of at least 1 GHz and a bandwidth greater than 100 MHz.    
     
     
         36 . The method as claimed in  claim 35  wherein the signal level of each output bit signal has: 
 (i) a first magnitude when the bit represented by that output bit signal has a particular digital value and that particular digital value is the same as the digital value of a bit represented by an immediately preceding output bit signal; and    (ii) a second magnitude when the bit represented by that output bit signal has the particular digital value and that particular digital value is different from the digital value of a bit represented by an immediately preceding output bit signal;    the first magnitude being lower than the second magnitude.    
     
     
         37 . The method as claimed in  claim 35  wherein the step of sending the output signal includes sending the output current pulses along a local signal path of a digital system to the receiver circuit.  
     
     
         38 . The method as claimed in  claim 37  wherein the steps of accepting the digital input signal and sending the output signal convey information between two or more elements of the digital system selected from the group consisting of processors, memories, and peripheral devices.