Semiconductor damascene trench and methods thereof

Abstract

A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and semiconductor devices embodying the cells are also provided. In accordance with one embodiment of the present invention, a memory device cell layout is provided comprising four active areas positioned between selected ones of the gates and local interconnects associated with different damascene trenches of the device.

1 . A memory device cell layout comprising: 
 a base substrate;    a first damascene trench formed on said base substrate, said first damascene trench having formed therein, first and second gates and first and second local interconnects by: 
 a gate oxide formed on said base substrate in said first and second gate areas of said first damascene trench,  
 a patterned mask formed over said memory device cell layout, wherein said patterned mask is arranged to expose at least a portion of said gate oxide within said first and second local interconnect areas of said first damascene trench during the etching process, and  
 at least one contact implant provided within a plug area in said base substrate, wherein said plug area is located at least partially beneath and in contact with said damascene local interconnect structures;  
   a second damascene trench formed on said base substrate, said second damascene trench having formed therein, first and second gates and first and second local interconnects by: 
 a gate oxide formed on said base substrate in said first and second gate areas of said second damascene trench,  
 a patterned mask formed over said memory device cell layout, wherein said patterned mask arranged to expose at least a portion of said gate oxide within said first and second local interconnect areas of said second damascene trench during the etching process, and  
 at least one contact implant provided within a plug area in said base substrate, wherein said plug area is located at least partially beneath and in contact with said damascene local interconnect structures;  
 a first active area between said first gate of said first damascene trench and said first local interconnect of said second damascene trench;  
   a second active area between said first local interconnect of said first damascene trench and said first gate of said second damascene trench;    a third active area between said second gate of said first damascene trench and said second local interconnect of said second damascene trench; and,    a fourth active area between said second local interconnect of said first damascene trench and said second gate of said second damascene trench.    
   
   
       2 . A memory device cell layout according to  claim 1 , further comprising a fifth active area coupling a first access transistor to said first local interconnect of said second damascene trench and a sixth active area coupling said second local interconnect of said first damascene trench to a second access transistor.  
   
   
       3 . A computer system comprising: 
 a bus;    a central processing unit coupled to said bus;    at least one input-output device coupled to said bus; and,    a memory device coupled to said bus, said memory device having a layout comprising:    a base substrate;    a first damascene trench formed on said base substrate, said first damascene trench having formed therein, first and second gates and first and second local interconnects by: 
 a gate oxide formed on said base substrate in said first and second gate areas of said first damascene trench,  
 a patterned mask formed over said memory device cell layout, wherein said patterned mask arranged to expose at least a portion of said gate oxide within said first and second local interconnect areas of said first damascene trench during the etching process, and  
 at least one contact implant provided within a plug area in said base substrate, wherein said plug area is located at least partially beneath and in contact with said damascene local interconnect structures;  
   a second damascene trench formed on said base substrate, said second damascene trench having formed therein, first and second gates and first and second local interconnects by: 
 a gate oxide formed on said base substrate in said first and second gate areas of said second damascene trench,  
 a patterned mask formed over said memory device cell layout, wherein said patterned mask arranged to expose at least a portion of said gate oxide within said first and second local interconnect areas of said second damascene trench during the etching process, and  
 at least one contact implant provided within a plug area in said base substrate, wherein said plug area is located at least partially beneath and in contact with said damascene local interconnect structures;  
   a first active area between said first gate of said first damascene trench and said first local interconnect of said second damascene trench;    a second active area between said first local interconnect of said first damascene trench and said first gate of said second damascene trench;    a third active area between said second gate of said first damascene trench and said second local interconnect of said second damascene trench; and,    a fourth active area between said second local interconnect of said first damascene trench and said second gate of said second damascene trench.