Reduced Cardbus Controller

Abstract

A cardbus controller is provided that reduces signal count and board area. In one exemplary embodiment, the controller is adapted to multiplex selected signals in a two PC Card system so that signal lines are not repeated. The selected signals may include common signals between two PC Cards. The controller may also include early detection circuitry, arbitration circuitry and power management circuitry to more effectively operate two PC Cards. In other exemplary embodiments, the invention provides a method of reducing the chip area of a PC Card controller integrated circuit by mapping an internal IDSEL signal to an external address line.

1 . A system for operating PC Cards comprising a controller adapted to control at least two independent PC Cards, said controller adapted to generate PC Card signal lines to control the operation of said at least two independent PC Cards and further adapted to multiplex selected ones of said signal lines so that said selected signal are operable with said at least two independent PC Cards.  
   
   
       2 . A system as claimed in  claim 1 , wherein said multiplexed signals are shared signals between said at least two PC Cards.  
   
   
       3 . A system as claimed in  claim 1 , further comprising a power switch, said controller adapted to generate a control signal to said power switch when at least one of said PC Cards is present, said power switch adapted to supply power to said at least on PC Card.  
   
   
       4 . A system as claimed in  claim 1 , further comprising at least two PC card sockets adapted to receive a respective one of said at least two PC Cards.  
   
   
       5 . A system as claimed in  claim 1 , wherein said selected signals comprise signals that are active when an operation is in progress on either said PC Card.  
   
   
       6 . A system as claimed in  claim 5 , wherein said selected signals comprise PCMCIA-16 address signals, as defined in the PC Card standard.  
   
   
       7 . A system as claimed in  claim 5 , wherein said selected signals comprise CardBus address/data signals, as defined in the PC Card standard.  
   
   
       8 . A system as claimed in  claim 1 , said controller also generating socket control signals for operating each of said PC Cards.  
   
   
       9 . A system as claimed in  claim 8 , wherein said socket control signal are selected from the group of PCMCIA-16 chip enable signals, PCMCIA-16 data signals, the CardBus clock signal, and the CardBus arbitration signals REQ# and GNT#.  
   
   
       10 . A system as claimed in  claim 1 , said controller further comprising early detection circuitry operable to provide early-detection notification of a the presence of second PC Card, said early detection circuitry also adapted to place the first PC Card in a hold condition, and wait for a power supply to be activated to the second PC Card.  
   
   
       11 . A system as claimed in  claim 1 , further comprising arbitration circuitry to arbitrate the control operations of said at least two PC Cards.  
   
   
       12 . A system as claimed in  claim 1 , further comprising power management circuitry to control power applied to the at least two PC Cards.