US2006282821A1PendingUtilityA1

Efficient subprogram return in microprocessors

42
Individually held — no corporate assignee on recordPriority: Jun 10, 2005Filed: Jun 10, 2005Published: Dec 14, 2006
Est. expiryJun 10, 2025(expired)· nominal 20-yr term from priority
Inventors:Erik K. RennoOyvind StromMorten A. Lund
G06F 9/3806G06F 9/30094G06F 9/30072G06F 9/323G06F 9/30054
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Claims

Abstract

A method and medium for performing subroutine return operations. Test operations are performed in parallel with other operations in a return operation. These test operations and the return operations are performed in response to a single instruction.

Claims

exact text as granted — not AI-modified
1 . A method for performing a subroutine return operation, the method comprising: 
 a) fetching an instruction which requires the return operation; and    b) setting status flags based on contents of a return value register in parallel with at least one other operation required to process the return operation, the status flags set before one of the following occurs: 
 i) contents of a return address register are moved into a program counter; or  
 ii) a return address is popped from a stack and into the program counter.  
   
   
   
       2 . The method of  claim 1  wherein either the contents of the return address register are moved into the program counter or a return address is popped from the stack and into the program counter only when a test operation determines return conditions are satisfied.  
   
   
       3 . The method of  claim 1  wherein the return operation is split into two micro-operations, one micro-operation for performing the return operation, the other micro-operation for performing a test operation.  
   
   
       4 . The method of  claim 1  wherein the status flags are set in parallel with writing contents of a return address register through an Arithmetic Logic Unit of a microprocessor.  
   
   
       5 . The method of  claim 1  wherein the status flags are set in parallel with routing control signals to data memory of a microprocessor past an Arithmetic Logic Unit of the microprocessor.  
   
   
       6 . The method of  claim 1  wherein steps a) and b) are performed in response to a single instruction.  
   
   
       7 . A processor-readable storage medium storing an instruction that, when executed by a processor, causes the processor to perform a method for performing a subroutine return operation, the method comprising: 
 a) fetching an instruction which requires the return operation; and    b) setting status flags based on contents of a return value register in parallel with at least one other operation required to process the return instruction, the status flags set before one of the following occurs: 
 i) contents of a return address register are moved into a program counter; or  
 ii) a return address is popped from a stack and into the program counter.  
   
   
   
       8 . The processor-readable storage medium of  claim 7  wherein either the contents of the return address register are moved into the program counter or a return address is popped from the stack and into the program counter only when a test operation determines return conditions are satisfied.  
   
   
       9 . The processor-readable storage medium of  claim 7  wherein the return operation is split into two micro-operations, one micro-operation for performing the return operation, the other micro-operation for performing a test operation.  
   
   
       10 . The processor-readable storage medium of  claim 7  wherein the status flags are set in parallel with writing contents of a return address register through an Arithmetic Logic Unit of a microprocessor.  
   
   
       11 . The processor-readable storage medium of  claim 7  wherein the status flags are set in parallel with routing control signals to data memory of the microprocessor past the Arithmetic Logic Unit of the microprocessor.  
   
   
       12 . The processor-readable storage medium of  claim 7 , the method further comprising flushing a pipeline before either the contents of the return address register or the return address is written into the program counter.  
   
   
       13 . The processor-readable storage medium of  claim 7  wherein steps a) and b) are performed in response to a single instruction.  
   
   
       14 . A method for performing a subroutine return operation comprising: 
 a) placing a return address into a program counter;    b) executing a test operation on a return value register, the test operation performed in parallel with at least one other operation required to process a return operation;    c) changing a flow of a program to a target address; and    d) performing steps a), b), and c) in response to a single instruction.    
   
   
       15 . The method of  claim 14  wherein the step of changing the flow of the program is performed only if the test operation determines return conditions are satisfied.  
   
   
       16 . The method of  claim 14  wherein the subroutine return operation is kept in an instruction decode stage for an additional cycle.  
   
   
       17 . The method of  claim 14  wherein status flags for the test operation are set in parallel with writing contents of a return address register through an Arithmetic Logic Unit of a microprocessor.  
   
   
       18 . The method of  claim 14  wherein status flags for the test operation are set in parallel with routing control signals to data memory of a microprocessor located downstream of an Arithmetic Logic Unit of the microprocessor.  
   
   
       19 . The method of  claim 14  further comprising loading multiple registers.  
   
   
       20 . The method of  claim 14  further comprising setting a return value in a return value register.  
   
   
       21 . A processor-readable storage medium storing an instruction that, when executed by a processor, causes the processor to perform a method for performing a subroutine return operation, the method comprising: 
 a) placing a return address into a program counter;    b) executing a test operation on a return value register, the test operation performed in parallel with at least one other operation required to process a return operation;    c) changing a flow of a program to a target address; and    d) performing steps a), b), and c) in response to a single instruction.    
   
   
       22 . The processor-readable storage medium of  claim 21  wherein the step of changing the flow of the program is performed only if the test operation determines return conditions are satisfied.  
   
   
       23 . The processor-readable storage medium of  claim 21  wherein the return operation is kept in an instruction decode stage for an additional cycle.  
   
   
       24 . The processor-readable storage medium of  claim 21  wherein status flags for the test operation are set in parallel with writing contents of a return address register through an Arithmetic Logic Unit of a microprocessor.  
   
   
       25 . The processor-readable storage medium of  claim 21  wherein status flags for the test operation are set in parallel with routing control signals to data memory of the microprocessor located downstream of Arithmetic Logic Unit of the microprocessor.  
   
   
       26 . The processor-readable storage medium of  claim 23 , the method further comprising loading multiple registers.  
   
   
       27 . The processor-readable storage medium of  claim 23 , the method further comprising setting a return value in a return value register.

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