Semiconductor memory device with debounced write control signal

Abstract

A semiconductor memory device having a memory cell array, an input buffer, an output buffer, and an input-output control circuit that receives a write control signal and controls the input and output buffers. The output buffer generates a commencement signal indicating commencement of output. A mask generating circuit generates a mask signal with delayed active-to-inactive transitions from the commencement signal. A masking circuit passes the write control signal to the input-output control circuit while the mask signal is inactive, and holds the write control signal in the write-disabling state while the mask signal is active. The mask signal prevents unintended writing of data in the memory cell array when the write control signal is contaminated by noise from the output buffer.

1 . A semiconductor memory device having a memory cell array that stores data received through an input buffer in a memory region designated by an address signal in a write operation and outputs data from the memory region designated by the address signal through an output buffer in a read operation, and having an input-output control circuit that controls the input buffer and the output buffer according to externally generated signals including at least a write control signal, wherein: 
 the output buffer generates a commencement signal having an active state and an inactive state, the active state indicating commencement of output; and    the semiconductor memory device comprises    a mask generating circuit for generating a mask signal having an active state and an inactive state from the commencement signal, the mask signal becoming active at least as soon as the commencement signal becomes active and remaining active until after the commencement signal has become inactive; and    a masking circuit for passing the write control signal to the input-output control circuit while the mask signal is inactive, and holding the write control signal input to the input-output control circuit in a write-disabling state while the mask signal is active.    
   
   
       2 . The semiconductor memory device of  claim 1 , wherein the mask generating circuit comprises: 
 a delay circuit for delaying the commencement signal to generate a delayed commencement signal; and    a logic circuit for performing a logic operation on the commencement signal and the delayed commencement signal to generate the mask signal.    
   
   
       3 . The semiconductor memory device of  claim 2 , wherein the delay circuit delays inactive-to-active transitions of the commencement signal by a first amount and delays active-to-inactive transitions of the commencement signal by a second amount greater than the first amount.  
   
   
       4 . The semiconductor memory device of  claim 3 , wherein the commencement signal is active high and the logic circuit is an OR gate.  
   
   
       5 . The semiconductor memory device of  claim 3 , wherein the delay circuit comprises: 
 a node;    a complementary pair of transistors switched on and off by the commencement signal, each of the transistors having one main electrode connected to said node;    at least one resistor connected in series between said main electrode of one of the transistors and said node;    at least one capacitor connected to said node; and    at least one inverter inserted between said node and the logic circuit.    
   
   
       6 . The semiconductor memory device of  claim 5 , wherein the delay circuit further comprises at least one progammable fuse coupled in parallel with the at least one resistor, for programming the second amount.  
   
   
       7 . The semiconductor memory device of  claim 5 , wherein the delay circuit further comprises at least one progammable fuse coupled in series with the at least one capacitor, for programming the second amount.  
   
   
       8 . The semiconductor memory device of  claim 1 , wherein the input-output control circuit generates an internal enable signal having an active state and an inactive state, the active state commanding the output buffer to commence output, and the mask generating circuit comprises: 
 a first delay circuit for delaying the internal enable signal to generate a delayed enable signal;    a second delay circuit for delaying the commencement signal to generate a delayed commencement signal; and    a logic circuit for performing a logic operation on the delayed enable signal and the delayed commencement signal to generate the mask signal.    
   
   
       9 . The semiconductor memory device of  claim 8 , wherein: 
 the first delay circuit delays inactive-to-active transitions of the internal enable signal by a first amount and delays active-to-inactive transitions of the internal enable signal by a second amount greater than the first amount; and    the second delay circuit delays inactive-to-active transitions of the commencement signal by a third amount and delays active-to-inactive transitions of the commencement signal by a fourth amount greater than the third amount.    
   
   
       10 . The semiconductor memory device of  claim 9 , wherein the first delay circuit includes a fuse-programmable resistor circuit and a fuse-programmable capacitor circuit for programming the second amount.  
   
   
       11 . The semiconductor memory device of  claim 9 , wherein the second delay circuit includes a fuse-programmable resistor circuit and a fuse-programmable capacitor circuit for programming the fourth amount.  
   
   
       12 . The semiconductor memory device of  claim 8 , wherein the internal enable signal and the commencement signal are active high and the logic circuit is an OR gate.  
   
   
       13 . The semiconductor memory device of  claim 1 , wherein the mask signal is active high and the masking circuit is a NOR gate.  
   
   
       14 . The semiconductor memory device of  claim 1 , wherein the write control signal is routed on a path substantially adjacent to the output buffer and is contaminated by noise caused by current flow in the output buffer.  
   
   
       15 . The semiconductor memory device of  claim 1 , wherein the semiconductor memory device is a dynamic random access memory.