Semiconductor device with interface circuit and method of configuring semiconductor devices

Abstract

Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell.

1 . A semiconductor integrated circuit device, comprising: 
 a core area; and    a plurality of I/O cells surrounding the core area, wherein each I/O cell comprises a plurality of features, wherein substantially all of the plurality of features are parallel to one another.    
   
   
       2 . The device of  claim 1 , wherein each of said I/O cells comprises a first cell edge arranged substantially perpendicular to a second cell edge, and further wherein at least one of said I/O cells has its first cell edge oriented substantially parallel to a horizontal edge of the device; and further wherein at least one other of said I/O cells has its second cell edge oriented substantially parallel to a vertical edge of the device.  
   
   
       3 . The device  claim 1 , wherein the I/O cell plurality of features comprise a plurality of I/O cell gates, and wherein at least 90% of said I/O cell gates are substantially parallel.  
   
   
       4 . The device of  claim 3 , wherein the plurality of I/O cells surround the core, and wherein the core comprises a plurality of core gates such that at least 90% of said core gates are substantially parallel to each other.  
   
   
       5 . The device of  claim 4 , wherein the at least 90% of said I/O cell gates are substantially parallel to at least 90% of said core gates.  
   
   
       6 . The device  claim 5 , wherein the plurality of core gates and the plurality of I/O cell gates comprise critically-dimensioned features.  
   
   
       7 . The device of  claim 6 , further comprising at least one circuit cell, wherein the at least one circuit cell comprises at least one circuit-cell feature, and wherein the at least one circuit cell is arranged within the core or within at least one of the I/O cells.  
   
   
       8 . A method of configuring a semiconductor integrated circuit comprising: 
 providing a core area comprising a plurality of core features; and    arranging a plurality of uniform I/O cells surrounding the core area, wherein each uniform I/O cell has substantially all features parallel to one another.    
   
   
       9 . The method of  claim 8 , wherein the I/O cell plurality of features comprise a plurality of I/O cell gates and the plurality of core features comprise a plurality of core gates, and further comprising: 
 arranging at least 90% of the I/O cell gates substantially parallel to one another; and    arranging at least 90% of the core gates substantially parallel to one other and further substantially parallel to the substantially parallel I/O cell gates.    
   
   
       10 . A semiconductor integrated circuit comprising: 
 a core, comprising a plurality of core device features arranged such that a majority of the plurality of core device features are substantially parallel; and    a plurality of I/O cells, each I/O cell comprising a plurality of I/O cell device features arranged such that a majority of the plurality of I/O cell device features in each I/O cell are substantially parallel.    
   
   
       11 . The circuit of  claim 10 , wherein substantially all of said core device features are substantially parallel and substantially all of said I/O cell device features are substantially parallel, and further wherein said core device features are substantially parallel to said I/O cell device features.  
   
   
       12 . The circuit of  claim 11 , wherein said substantially all of the plurality of core device features and substantially all of the plurality of I/O cell device features comprise critically-dimensioned features.  
   
   
       13 . The circuit of  12 , further comprising at least one circuit cell, wherein the at least one circuit cell comprises circuit cell device features, and wherein the at least one circuit cell is arranged within the core or within at least one I/O cell.  
   
   
       14 . The circuit of  claim 11 , wherein the plurality of I/O cells further comprise comprises a plurality of horizontal I/O cells and a plurality of vertical I/O cells, wherein said plurality of horizontal I/O cells and said plurality of vertical I/O cells have dissimilar layouts.  
   
   
       15 . The circuit of  claim 13 , wherein the circuit cell device features comprise at least one feature arranged perpendicular to said core device features or to said I/O cell device features.  
   
   
       16 . The circuit of  claim 11 , wherein the plurality of I/O cells further comprise a plurality of horizontal I/O cells and a plurality of vertical I/O cells, and wherein said plurality of horizontal I/O cells are translationally disposed with respect to said plurality of vertical I/O cells.  
   
   
       17 . The circuit of  claim 10 , wherein said core device features and said I/O cell device features comprise gates.  
   
   
       18 . The circuit of  claim 11 , wherein said I/O cells have a substantially square footprint.  
   
   
       19 . A method of configuring a semiconductor integrated circuit device, comprising: 
 orienting a plurality of core device features in a core substantially parallel to one another; and    orienting a plurality of I/O cell device features in an I/O cell substantially parallel to one another, wherein said core device features and said I/O cell device features are arranged within a common layer.    
   
   
       20 . A semiconductor integrated circuit device, comprising: 
 a core comprising a plurality of core device features arranged such that at least 90% of said core device features are substantially parallel; and    a plurality of I/O cells having substantially matching device feature layouts, each I/O cell comprising a plurality of I/O cell device features arranged such that at least 90% of said I/O cell device features are substantially parallel.    
   
   
       21 . The device of  claim 20 , wherein each I/O cells comprises a first cell edge arranged substantially perpendicular to a second cell edge, wherein a first cell edge of a first I/O cell corresponds to a first cell edge of a second I/O cell, wherein at least one of said I/O cells is oriented along a horizontal edge of the device such that a first cell edge of said at least one horizontal I/O cell is substantially parallel to a horizontal edge of the device; and wherein at least one of said I/O cells along a vertical edge of the device is oriented such that a second cell edge of said at least one vertical I/O cell is substantially parallel to a vertical edge of the device.  
   
   
       22 . The device of  claim 21 , wherein said parallel core device features are parallel to said parallel I/O device features, and wherein said parallel features are arranged on a common layer.  
   
   
       23 . The device of  claim 22 , further comprising at least two circuit cells, wherein the at least two circuit cells comprise circuit-cell device features, wherein at least one circuit cell is arranged within a horizontal I/O cell, and wherein at least one circuit cell is arranged within a vertical I/O cell.  
   
   
       24 . The device of  claim 23 , wherein said horizontal I/O cell and said vertical I/O cell are symmetrically disposed or translationally disposed.  
   
   
       25 . The device of  claim 24 , further comprising at least one circuit cell, wherein the at least one circuit cell comprises at least one circuit-cell device feature, and wherein the at least one circuit cell is arranged within the core.  
   
   
       26 . A patterning device used to produce layer-specific semiconductor device features, said patterning device comprising: 
 a core area, comprising a plurality of critically-dimensioned core features, wherein at least 90% of said critically-dimensioned core features are configured in parallel; and    an I/O cell area bordering the core area, wherein the I/O cell area comprises a plurality of critically-dimensioned I/O cell features, wherein substantially all critically-dimensioned I/O cell features are configured in parallel.    
   
   
       27 . The patterning device of  claim 26 , wherein substantially all critically-dimensioned core features are configured in parallel and substantially all critically-dimensioned I/O cell features are configured in parallel.  
   
   
       28 . The patterning device of  claim 27 , wherein the critically-dimensioned core features are substantially parallel to the critically-dimensioned I/O cell features.  
   
   
       29 . The patterning of  claim 28 , further comprising at least one circuit cell, wherein the at least one circuit cell has at least one non-critically-dimensioned device feature.  
   
   
       30 . The patterning device of  claim 29 , wherein the I/O cell area comprises at least one horizontal I/O cell and at least one vertical I/O cell, wherein each I/O cell comprises a circuit cell, and wherein said I/O cells have substantially matching feature layouts such that the at least one horizontal I/O cell layout is translationally disposed from the at least one vertical I/O cell layout.  
   
   
       31 . The patterning device as recited in  claim 29 , wherein the I/O cell area comprises at least one horizontal I/O cell and at least one vertical I/O cell, wherein each I/O cell comprises a circuit cell, and wherein said I/O cells have substantially matching feature layouts such that the at least one horizontal I/O cell layout is in point symmetry with the at least one vertical I/O cell layout.