Address window support for direct memory access translation

Abstract

A apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.

1 . An apparatus comprising a remapping circuit to facilitate access of one or more input/output (I/O) devices to a memory device using direct memory access (DMA) transactions, the remapping circuit including a first translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.  
   
   
       2 . The apparatus of  claim 1  further comprising a second translation mechanism to perform memory address translations for I/O DMA transactions via at least one of single-level page tables and multi-level page tables.  
   
   
       3 . The apparatus of  claim 1  wherein the first translation mechanism includes an address window pointer table (AWPTR) to perform the address window-based translations.  
   
   
       4 . The apparatus of  claim 3  wherein the AWPTR comprises at least one entry including a base address of an address window page table (AWPT) for at least one address window (AW).  
   
   
       5 . The apparatus of  claim 4  wherein each AWPTR entry is tagged with a device ID indicating an I/O device to which an associated AW is allocated.  
   
   
       6 . The apparatus of  claim 5  wherein the device ID further includes information indicating at least one of a bus, a device, and a function within the device.  
   
   
       7 . The apparatus of  claim 4  wherein each AWPT entry provides a translation for a 4 KB slot within the AW.  
   
   
       8 . The apparatus of  claim 4  wherein each AWPT entry includes access control bits specifying if read accesses or write accesses are allowed to a device-physical address used to access the AWPT entry.  
   
   
       9 . A method comprising: 
 receiving a direct memory access (DMA) request at a remapping circuit from a requesting input/output (I/O) device;    determining if the DMA request is permitted to complete; and    translating a device-physical address (DPA) to a host-physical address (HPA) in memory if the access is permitted.    
   
   
       10 . The method of  claim 9  wherein determining if the DMA request is permitted to complete comprises: 
 calculating a requested address window (AW) associated with the DPA;    determining if the requested AW is bound to the remapping circuit; and    determining if the requested AW is bound to the requesting I/O device.    
   
   
       11 . The method of  claim 10  wherein a translation fault occurs if it is determined that the requested AW is not bound to the requesting I/O device.  
   
   
       12 . The method of  claim 10  wherein the translation fault occurs if it is determined that the requested AW is not bound to the remapping circuit.  
   
   
       13 . The method of  claim 9  further comprising: 
 finding an associated AW pointer table entry index for the DPA; and    looking up the AW pointer table entry at the index.    
   
   
       14 . The method of  claim 13  further comprising determining whether the AW pointer table entry is tagged with a device ID corresponding to the requesting I/O device.  
   
   
       15 . The method of  claim 13  further comprising accessing an AW page table entry (AWPTE) in memory associated with the AW pointer table entry and the DPA.  
   
   
       16 . The method of  claim 15  further comprising calculating the HPA associated with the DPA using the AWPTE.  
   
   
       17 . The method of  claim 16  further comprising: 
 determining if the DMA request is allowed to complete based on at least one permission bit in the AWPTE and a type of the DMA request; and    preventing the completion of the DMA request if at the least one permission bit does not allow the type of the DMA request.    
   
   
       18 . The method of  claim 9  further comprising caching the completed translation.  
   
   
       19 . A computer system comprising: 
 a main memory device;    one or more input/output (I/O) devices to access the memory device via direct memory access (DMA); and    a memory controller, coupled to the memory device, having a DMA remapping circuit to facilitate the access of the one or more I/O devices to the memory device, the DMA remapping circuit comprising: 
 a first translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.  
   
   
   
       20 . The computer system of  claim 19  further comprising a second translation mechanism to perform memory address translations for I/O DMA transactions via at least one of single-level page tables and multi-level page tables.  
   
   
       21 . The computer system of  claim 19  wherein the memory device is subdivided into at least one address windows (AWs).  
   
   
       22 . The computer system of  claim 21  wherein the memory device further comprises an AW page table (AWPT) that defines a device-physical address (DPA) to host-physical address (HPA) translation.  
   
   
       23 . The computer system of  claim 22  wherein the AWPT comprises at least one AW page table entry (AWPTE), said AWPTE providing a translation for at least one address within the AW.  
   
   
       24 . The computer system of  claim 21  wherein each of the at least one AWs are bound to an I/O device.  
   
   
       25 . The computer system of  claim 22  wherein the first translation mechanism includes a table (AWPTR) to perform the address window-based translations.  
   
   
       26 . The computer system of  claim 22  wherein the AWPTR comprises at least one entry, said entry including a base of the AWPT for a particular AW.  
   
   
       27 . The computer system of  claim 26  wherein each AWPTR entry is tagged with a device ID indicating an I/O device to which an associated AW is allocated.