Layered microlens structures and devices

Abstract

A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an angle away from normal to form upper lens layers that increase the effective focal length of the microlens structure. The upper lens layers can be deposited in an aspherical shape with radii of curvature longer than the lower lens layers. As a result, small microlenses can be provided with longer focal lengths. The microlenses are arranged in arrays for use in imaging devices.

1 - 17 . (canceled)  
     
     
         18 . A microlens array comprising: 
 an array of lower lens layers; and    an array of upper lens layers over the array of lower lens layers, wherein adjacent lower lens layers are separated by gaps, the gaps being at least partially filled by the respective upper lens layers.    
     
     
         19 . A microlens array according to  claim 18 , wherein the upper lens layers are formed by deposition directly on respective ones of the lower lens layers.  
     
     
         20 . A microlens array according to  claim 18 , wherein the upper lens layers are aspherical.  
     
     
         21 . A microlens array according to  claim 18 , wherein the upper lens layers have a thickness that is greater near a bottom portion of the lower lens layers than at a top portion of respective ones of the lower lens layers.  
     
     
         22 . A microlens array according to  claim 18 , in which the lower lens layers have a spherical shape  
     
     
         23 . (canceled)  
     
     
         24 . An imaging integrated circuit (IC) comprising: 
 an imaging array including a plurality of photosensitive regions; and    a plurality of lens structures provided on the imaging array, each lens structure being over a respective one of the photosensitive regions, each lens structure including upper and lower lens layers, wherein adjacent lower lens layers are separated by gaps, the gaps being at least partially filled by the respective upper lens layers.    
     
     
         25 . An imaging IC as in  claim 24 , wherein each of the photosensitive regions includes a photodiode.  
     
     
         26 . An imaging IC as in  claim 24 , further comprising circuitry for row and column selection.  
     
     
         27 . An imaging IC as in  claim 24 , wherein the imaging IC is a CMOS imager.  
     
     
         28 . An imaging IC as in  claim 24 , wherein the imaging IC is a CCD imager.  
     
     
         29 - 39 . (canceled)  
     
     
         40 . A microlens array comprising: 
 an array of lower lens layers, each lower lens layer having a spherical cross-sectional shape; and    an array of upper lens layers over the array of lower lens layers, each upper lens layer having an aspherical cross-sectional shape different from the spherical cross-sectional shape.    
     
     
         41 . A microlens array according to  claim 40 , wherein the upper lens layers have a thickness that is greater near a bottom portion of the lower lens layers than at a top portion of the lower lens layers.  
     
     
         42 . A microlens array according to  claim 40 , in which the lower lens layers'upper surfaces have a smaller radius of curvature than the upper lens layers'upper surfaces.  
     
     
         43 . An imaging integrated circuit (IC) comprising: 
 an imaging array including a plurality of photosensitive regions; and    a plurality of lens structures provided on the imaging array, each lens structure being over a respective one of the photosensitive regions, the lens structures including upper and lower lens layers, each lower lens layer having a spherical cross-sectional shape, and each upper lens layer having an aspherical cross-sectional shape different from the spherical cross-sectional shape.    
     
     
         44 . An imaging IC as in  claim 43 , wherein each of the photosensitive regions includes a photodiode.  
     
     
         45 . An imaging IC as in  claim 43 , further comprising circuitry for row and column selection.  
     
     
         46 . An imaging IC as in  claim 43 , wherein the imaging IC is a CMOS imager.  
     
     
         47 . An imaging IC as in  claim 43 , wherein the imaging IC is a CCD imager.  
     
     
         48 . An image processing system comprising: 
 a processor coupled to a bus; and    an imaging integrated circuit (IC) coupled to the bus, the imaging IC comprising: 
 an imaging array containing a plurality of photosensitive regions; and  
 a plurality of lens structures provided on the imaging array, each lens structure being over a respective one of the photosensitive regions, the lens structures including upper and lower lens layers, wherein adjacent lower lens layers are separated by gaps, the gaps being at least partially filled by the respective upper lens layers.  
   
     
     
         49 - 67 . (canceled)