An isolation region for use in a semiconductor device

Abstract

An isolation region for use in a semiconductor device is formed in a p-type silicon substrate. An n-type silicon layer is disposed on the p-type silicon substrate, wherein the n-type silicon layer is separated by an oxidized porous silicon layer. At least a portion of the oxidized porous silicon layer is recessed below the n-type silicon layer. The isolation region may be formed between neighboring semiconductor devices such as, for example, transistors.

1 . An isolation region for use in a semiconductor device comprising: 
 a p-type silicon substrate; and    an n-type silicon layer disposed on the p-type silicon substrate, the n-type silicon layer being separated by an oxidized porous silicon layer, wherein at least a portion of the oxidized porous silicon layer is recessed below the n-type silicon layer.    
   
   
       2 . The isolation region of  claim 1 , wherein the isolation region is formed between neighboring semiconductor devices.  
   
   
       3 . The isolation region of  claim 2 , wherein the neighboring semiconductor devices comprise transistors.  
   
   
       4 . The isolation region of  claim 1 , wherein at least a portion of the oxidized porous silicon layer projects above the n-type silicon layer.  
   
   
       5 . The isolation region of  claim 1 , wherein an upper surface of the oxidized porous silicon layer is substantially planar with an upper surface of the n-type silicon layer.  
   
   
       6 . The isolation region of  claim 1 , wherein at least a portion of the oxidized porous silicon layer is under compression.  
   
   
       7 . The isolation region of  claim 1 , wherein at least a portion of the isolation region has an hour glass cross-sectional profile.