Communication registers for processing elements

Abstract

Various embodiments of the invention relate to communicating data between a number of processing elements (PEs) of a signal processor, using a plurality of communication registers (CCRs). For instance, a plurality of the CCRs can be shared by and mapped to the address space of each PE, where each CCR couples a first of the PEs to every other one of the PEs. Moreover, each CCR can include a data payload field and a data valid field to indicate a target PE to read the data in the data payload field. Thus, data can be written to a selected CCR by a PE and stored in the selected CCR to be read by at least one target PE.

1 . A system comprising: 
 a plurality of image signal processors (ISPs), each of the ISPs coupled to at least two other of the ISPs, each of the ISPs including a plurality of communication registers and a plurality of processing elements;    a random access memory coupled to at least one of the plurality of ISPs; and    wherein each of the plurality of communication registers is mapped directly to an address space of each processing element of the plurality.    
   
   
       2 . The system of  claim 1 , wherein each of the plurality of communication registers couples a first of the plurality of processing elements to every other one of the plurality of processing elements.  
   
   
       3 . The system of  claim 1 , wherein the plurality of communication registers are shared by the addressing space of each processing element of the plurality of processing elements.  
   
   
       4 . The system of  claim 1 , wherein a first of the plurality of processing elements is a memory command handler to read and write data between the plurality of communication registers and a second memory, and a second of the plurality of processing elements is a plurality of hardwired accelerators.  
   
   
       5 . The system of  claim 1 , further comprising a write control circuit to write data to a selected communication register, the data to be stored in the selected communication register and to be read by at least one selected processing element.  
   
   
       6 . A method comprising: 
 indicating at least one selected processing element of a plurality of processing elements to read data to be written to a selected communication register of a plurality of communication registers mapped to the addressing space of each processing element of the plurality of processing elements;    writing the data to the selected communication register; and    providing access to the data to the selected processing elements.    
   
   
       7 . The method of  claim 6 , wherein each of the plurality of communication registers couples a first of the plurality of processing elements to every other one of the plurality of processing elements.  
   
   
       8 . The method of  claim 6 , wherein the plurality of communication registers are shared by the addressing space of each processing element of the plurality of processing elements.  
   
   
       9 . The method of  claim 6  further comprising: 
 the selected processing elements reading the data.    
   
   
       10 . The method of  claim 6 , wherein writing comprises: 
 writing the data to an address defined within the writing processing elements addressing space that maps directly to the selected communication register.    
   
   
       11 . The method of  claim 6 , wherein indicating includes setting at least one of a plurality of data valid bits in the data to be written, each of the plurality of data valid bits corresponding to one of the plurality of processing elements, the set data valid bits identifying the at least one selected processing element.  
   
   
       12 . The method of  claim 11 , further comprising: 
 the selected processing elements reading the data, if the data has a set data valid bit identifying the selected processing elements.    
   
   
       13 . The method of  claim 11 , wherein a first of the processing elements sets the set data valid bits, and a second of the processing elements reads the data, if one of the set data valid bits of the stored data identifies the second of the processing elements.  
   
   
       14 . The method of  claim 13 , further comprising: 
 the second of the processing elements returning a data valid reset signal to the selected communication register, if the second of the processing elements has completed reading the data; and    resetting the one of the set data valid bits of the data identifying the second of the processing elements.    
   
   
       15 . The method of  claim 11 , further comprising asserting a data write stall signal to the plurality of processing elements to stop the plurality of processing elements from writing a second data to the selected communication register, if the data includes a set data valid bit.  
   
   
       16 . The method of  claim 11 , further comprising writing a second data to the selected communication register, if the data does not include a set data valid bit.  
   
   
       17 . The method of  claim 6 , wherein providing access further comprises: 
 broadcasting the data to the address defined within the writing processing elements addressing space of each of the processing elements.