Electrostatic discharge protection circuit

Abstract

The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.

1 . An electrostatic discharge (ESD) protection circuit, comprising: 
 a silicon controlled rectifier having a plurality of SCR fingers, where each SCR finger comprises:    at least one interspersed high-doped first region formed within a first lightly doped region; at least one interspersed high-doped second region formed within a second lightly doped region;    at least one boost circuit connected at the high-doped second region, at least one first trigger-tap coupled to the second lightly doped region for supplying a trigger current to said SCR finger; and    at least one first low-ohmic connection respectively coupled between the at least one first trigger tap of each SCR finger.    
     
     
         2 . The circuit of  claim 1  wherein said boost circuit comprises at least one of diode, MOS, resistor, capacitor and inductor.  
     
     
         3 . The circuit of  claim 1  further comprising 
 a first voltage potential coupled to the at least one high-doped first region of each SCR finger and to protected circuitry; and a second voltage potential coupled to the at least second high-doped second region of each SCR finger.    
     
     
         4 . The circuit of  claim 1  further comprising: 
 at least one second trigger-tap coupled to the first lightly doped region of each SCR finger, and    at least one second low-ohmic connection respectively coupled between the at least one second trigger tap of each SCR finger.    
     
     
         5 . The circuit of  claim 1  further comprising at least a second boost circuit connected at the high-doped second region.  
     
     
         6 . An electrostatic discharge (ESD) protection circuit, comprising: 
 a silicon controlled rectifier having a plurality of SCR fingers, each SCR finger including at least one trigger tap connected to each SCR finger for supplying trigger current to each SCR finger and at least one boost circuit connected to each SCR finger; and    at least one low-ohmic connection electrically coupling the at least one trigger tap of each SCR finger to a common triggering voltage potential.    
     
     
         7 . The circuit of  claim 6  wherein said boost circuit provides an additional voltage drop at the trigger tap as the trigger current runs through the boost circuit.  
     
     
         8 . The circuit of  claim 6  wherein said boost circuit comprises at least one of diode, MOS, resistor, capacitor and inductor.  
     
     
         9 . An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC), the ESD protection circuit comprising: 
 at least a first silicon controlled rectifier having at least one first anode coupled to a first voltage potential and at least one first cathode coupled to a second voltage potential;    at least a second silicon controlled rectifier having at least one second anode coupled to the a third voltage potential and at least one second cathode coupled to a fourth voltage potential; said first and second cathodes having at least one first high-doped region and said first and second anodes having at least one second high-doped region;    at least one first trigger-tap, disposed proximate to the at least one first high-doped region of the first cathode; at least one second trigger-tap, disposed proximate to the at least one first high-doped region of the second cathode; and    at least one first low ohmic connection coupled between said first trigger tap and second trigger-tap.    
     
     
         10 . The circuit of  claim 9  wherein said first voltage potential and said third voltage potential have substantially equivalent values.  
     
     
         11 . The circuit of  claim 9  wherein said second voltage potential and said fourth voltage potential have substantially equivalent values.  
     
     
         12 . The circuit of  claim 9  wherein said first and third voltage potentials have substantially equivalent values and said second and fourth voltage potentials have substantially equivalent values.  
     
     
         13 . The circuit of  claim 9  further comprising: 
 at least one third trigger-tap, disposed proximate to the at least one second high-doped region of the first anode;    at least one fourth trigger-tap, disposed proximate to the at least one second high-doped region of the second anode; and    at least one second low ohmic connection coupled between said third and fourth trigger-tap.    
     
     
         14 . The circuit of  claim 9  further comprising a first external on-chip triggering device coupled to the at least first and second trigger tap.  
     
     
         15 . The circuit of  claim 9  further comprising a second external on-chip triggering device coupled to the at least third and fourth trigger tap.  
     
     
         16 . An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC), the ESD protection circuit comprising: 
 at least a first silicon controlled rectifier having at least one first anode coupled to a first voltage potential and at least one first cathode coupled to a second voltage potential;    at least a second silicon controlled rectifier having at least one second anode coupled to the first voltage potential and at least one second cathode coupled to the second voltage potential said first and second cathodes having at least one first high-doped region and said first and second anodes having at least one second high-doped region;    at least one first boost circuit connected at the first high-doped region of the first cathode and at least one second boost circuit connected at the first high-doped region of the second cathode,    at least one first trigger-tap, disposed proximate to the at least one first high-doped region of the first cathode;    at least one second trigger-tap, disposed proximate to the at least one first high-doped region of the second cathode; and    at least one first low ohmic connection coupled between said first and second trigger tap.    
     
     
         17 . The circuit of  claim 16  wherein said first and second boost circuits comprises at least one of diode, MOS, resistor, capacitor and inductor.  
     
     
         18 . An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC), the ESD protection circuit comprising: 
 at least a first silicon controlled rectifier having at least one first anode coupled to a first voltage potential and at least one first cathode coupled to a second voltage potential;    at least a second silicon controlled rectifier having at least one second anode coupled to the first voltage potential and at least one second cathode coupled to the second voltage potential; said first and second cathodes having at least one first high-doped region and said first and second anodes having at least one second high-doped region;    at least one first boost circuit connected at the second high-doped region of the first anode and at least one second boost circuit connected at the second high-doped region of the second anode, at least one first trigger-tap, disposed proximate to the at least one second high-doped region of the first anode; and    at least one second trigger-tap, disposed proximate to the at least one second high-doped region of the second anode; said first and second trigger-tap connected together with low ohmic connection.    
     
     
         19 . The circuit of  claim 18  wherein said first and second boost circuits comprises at least one of diode, MOS, resistor, capacitor and inductor.  
     
     
         20 . An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC), the ESD protection circuit comprising: 
 at least a first silicon controlled rectifier having at least one first anode coupled to a first voltage potential and at least one first cathode coupled to a second voltage potential;    at least a second silicon controlled rectifier having at least one second anode coupled to the first voltage potential and at least one second cathode coupled to the second voltage potential; said first and second cathodes having at least one first high-doped region and said first and second anodes having at least one second high-doped region;    at least one first trigger-tap, disposed proximate to the at least one first high-doped region of the first cathode;    at least one second trigger-tap, disposed proximate to the at least one first high-doped region of the second cathode; and    at least one boost circuit connected between the first and the second trigger tap.    
     
     
         21 . The circuit of  claim 20  wherein said boost circuit comprises at least one of diode, MOS, resistor, capacitor and inductor.  
     
     
         22 . An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC), the ESD protection circuit comprising: 
 at least a first silicon controlled rectifier having at least one first anode coupled to a first voltage potential and at least one first cathode coupled to a second voltage potential;    at least a second silicon controlled rectifier having at least one second anode coupled to the first voltage potential and at least one second cathode coupled to the second voltage potential; said first and second cathodes having at least one first high-doped region and said first and second anodes having at least one second high-doped region;    at least one first trigger-tap, disposed proximate to the at least one second high-doped region of the first anode;    at least one second trigger-tap, disposed proximate to the at least one second high-doped region of the second anode; and    at least one boost circuit connected between the first and the second trigger tap,    
     
     
         23 . The circuit of  claim 22  wherein said boost circuit comprises at least one of diode, MOS, resistor, capacitor and inductor.  
     
     
         24 . An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC), the ESD protection circuit comprising: 
 at least a first silicon controlled rectifier (SCR) including at least one first region having a first conductive type formed in a second region having a second conductive type opposite to the first conductive type and at least one third region having a second conductive type formed in a fourth region having a first conductive type, said first region coupled to a first voltage potential and said third region coupled to a second voltage potential; and    at least a second silicon controlled rectifier (SCR) including at least one fifth region having a first conductive type formed in a sixth region having a second conductive type, and at least one seventh region having a second conductive type formed in a eighth region having a first conductive type, said fifth region coupled to a third voltage potential and said seventh region coupled to a fourth voltage potential;    
     
     
         25 . The circuit of  claim 24  wherein the second region of the first SCR forms one region with the sixth region of the second SCR.  
     
     
         26 . The circuit of  claim 24  wherein the fourth region of the first SCR forms one region with the eighth region of the second SCR.  
     
     
         27 . The circuit of  claim 25  wherein the fourth region of the first SCR forms one region with the eighth region of the second SCR.  
     
     
         28 . The circuit of  claim 24  further comprising at least one trigger tap disposed in at least one of the first region of the first SCR and the fifth region of the second SCR.  
     
     
         29 . The circuit of  claim 24  wherein at least one first trigger-tap disposed in at least one of the second region of the first SCR and the sixth region of the second SCR.  
     
     
         30 . The circuit of  claim 24  wherein at least one first trigger tap disposed in at least one of the fourth region of the first SCR and the eighth region of the second SCR.  
     
     
         31 . An electrostatic discharge (ESD) protection circuit, comprising: 
 a silicon controlled rectifier having a plurality of SCR fingers, each SCR finger including at least one trigger tap connected to each of the SCR finger for supplying trigger current to each of the SCR finger; and    at least one low-ohmic connection electrically coupling the at least one trigger tap of each of the SCR finger to a common triggering voltage potential, thereby coupling the plurality of the SCR fingers.    
     
     
         32 . An electrostatic discharge (ESD) protection circuit, comprising: 
 a first clamp coupled between a first power and a ground line; 
 a second clamp coupled between a second power and the ground line; wherein said first and second clamps are coupled together to enable one of said first and second clamps to trigger the other of said first and second clamps