Gate driver circuit and display device having the same

Abstract

A gate driver circuit includes a driving section and a wiring section. The wiring section receives a plurality of signals from an external device. The driving section includes a plurality of stages providing a plurality of gate lines with a gate signal. The wiring section includes first and second signal wirings. The first signal wiring is disposed adjacent to a first side of the driving section, where the first side receives the signals from the wiring section. The second signal wiring is disposed adjacent to a portion that is disposed at an outer side of the driving section and the first signal wiring. Therefore, a signal applied to the first signal wiring is prevented from being delayed by the second signal wiring. Furthermore, a distortion of signal applied to the gate driver and a maloperation of the gate driver are prevented.

1 . A gate driver circuit comprising: 
 a driving section having a plurality of stages providing a plurality of gate lines with a gate signal;    a first wiring section disposed at a first side of the driving section, the first wiring section receiving a plurality of signals; and    a second wiring section disposed at a side of a region having the driving section and the first wiring section formed therein.    
   
   
       2 . The gate driver circuit of  claim 1 , wherein the second wiring section is disposed between the driving section and the plurality of gate lines.  
   
   
       3 . The gate driver circuit of  claim 2 , wherein the second wiring section extends along a second side of the driving section and delivers a start signal to a first input terminal of a first stage in the plurality of stages and delivers the start signal to a second input terminal of a last stage in the plurality of stages.  
   
   
       4 . The gate driver circuit of  claim 1 , wherein the second wiring section delivers a start signal to the driving section, and the second wiring section is insulated from the first wiring section.  
   
   
       5 . The gate driver circuit of  claim 1 , wherein the first wiring section comprises at least one first signal wiring electrically connected to at least two stages among the stages, 
 the second wiring section comprises a second signal wiring electrically connected to a first stage among the stages, and a third signal wiring electrically connected to a last stage among the stages, and    the at least one first signal wiring is disposed between the third signal wiring and the driving section.    
   
   
       6 . The gate driver circuit of  claim 5 , wherein the second signal wiring and the third signal wiring are electrically insulated from the at least one first signal wiring.  
   
   
       7 . A gate driver circuit comprising: 
 a wiring section receiving a plurality of signals from an external device; and    a driving section having a plurality of stages and having a first side and a second side, the first side of the driving section receiving the plurality of signals from the wiring section, and the second side of the driving section providing a plurality of gate lines with a gate signal,    wherein the wiring section comprises: 
 a first signal wiring disposed adjacent to the first side of the driving section; and  
 a second signal wiring disposed adjacent to the second side of the driving section.  
   
   
   
       8 . The gate driver circuit of  claim 7 , wherein the second signal wiring is additionally disposed adjacent to the first signal wiring.  
   
   
       9 . The gate driver circuit of  claim 7 , wherein the first signal wiring comprises: 
 a first clock wiring transferring a first clock signal to the plurality of stages;    a second clock wiring transferring a second clock signal to the plurality of stages, the second clock signal having opposite phase to the first clock signal; and    a reference voltage wiring transferring a reference voltage to the plurality of stages.    
   
   
       10 . The gate driver circuit of  claim 9 , wherein the first signal wiring further comprises a reset wiring resetting the stages by providing the stages with a gate signal outputted from a last stage of the plurality of stages.  
   
   
       11 . The gate driver circuit of  claim 7 , wherein the second signal wiring is a start signal wiring receiving a start signal and transferring the start signal to a first stage and a last stage of the plurality of stages.  
   
   
       12 . The gate driver circuit of  claim 11 , wherein the start signal wiring is electrically insulated from the first signal wiring.  
   
   
       13 . The gate driver circuit of  claim 11 , further comprising an insulating layer disposed between the plurality of gate lines and the start signal wiring, wherein the insulating layer electrically insulates the plurality of gate lines from the start signal wiring, the start signal wiring crossing the plurality of gate lines.  
   
   
       14 . The gate driver circuit of  claim 13 , wherein a width of the start signal wiring is relatively thinner in cross portions between the plurality of gate lines and the start signal wiring than in other areas of the start signal wiring.  
   
   
       15 . A gate driver circuit comprising: 
 a driving section providing a gate signal;    a first wiring section receiving a plurality of signals;    at least one connecting wiring connecting the first wiring section to the driving section, the at least one connecting wiring transmitting the plurality of signals to the driving section; and,    a start signal wiring transmitting a start signal to a first stage of the plurality of stages, wherein the start signal wiring does not cross the at least one connecting wiring.    
   
   
       16 . The gate driver circuit of  claim 15 , wherein the start signal wiring further transmits a start signal to a last stage of the plurality of stages.  
   
   
       17 . The gate driver circuit of  claim 16 , wherein the start signal wiring includes a first start signal wiring transmitting the start signal to the first stage of the plurality of stages, and a second start signal wiring transmitting the start signal to the last stage of the plurality of stages.  
   
   
       18 . The gate driver circuit of  claim 17 , wherein the first wiring section is disposed between the second start signal wiring and the driving section.  
   
   
       19 . The gate driver circuit of  claim 18 , wherein the first start signal wiring is electrically connected to the second start signal wiring, and the first start signal wiring is substantially parallel to the at least one connecting wiring.  
   
   
       20 . The gate driver circuit of  claim 18 , wherein the first start signal wiring is separated from the second start signal wiring by the first wiring section.  
   
   
       21 . The gate driver circuit of  claim 16 , wherein the driving section includes a first side receiving the plurality of signals from the at least one connecting wiring, and a second side outputting the gate signal, wherein the first wiring section is disposed on the first side of the driving section and the start signal wiring extends adjacent the second side of the driving section.  
   
   
       22 . The gate driver circuit of  claim 15 , wherein the first wiring section includes a first clock wiring transferring a first clock signal to the driving section via a first connecting wiring, and a second clock wiring transferring a second clock signal to the driving section via a second connecting wiring, wherein the second clock signal has an opposite phase to the first clock signal.  
   
   
       23 . A display device comprising: 
 a display panel having a plurality of gate lines and a plurality of data lines, and displaying an image;    a gate driver circuit having a wiring section receiving a plurality of signals from an external device, and a driving section having a plurality of stages and having a first side and a second side, the driving section receiving the plurality of signals from the wiring section through the first side, and the driving section transmitting a gate signal to the plurality of gate lines through the second side; and    a data driver circuit providing the data lines with a data signal;    wherein the wiring section includes: 
 a first signal wiring disposed at the first side of the driving section; and  
 a second signal wiring disposed at the second side of the driving section.  
   
   
   
       24 . The display device of  claim 23 , wherein the second signal wiring is a start signal wiring receiving a start signal and transferring the start signal to a first stage and a last stage of the plurality of stages.  
   
   
       25 . A display device comprising: 
 a display panel displaying an image and including an array substrate having a plurality of gate lines and a plurality of data lines, the array substrate receiving a gate signal and a data signal and facing an opposite substrate;    a gate driver circuit having a wiring section receiving a plurality of signals from an external device, and circuit section including a plurality of stages electrically connected one after another to each other, the plurality of stages receiving a plurality of signals from the wiring section and sequentially applying the gate signal to the plurality of gate lines; and    a data driver circuit outputting a data signal to the plurality of data lines;    wherein the wiring section includes: 
 at least one first signal wiring electrically connected to at least two stages of the plurality of stages;  
 a second signal wiring electrically connected to a first stage of the plurality of stages; and  
 a third signal wiring electrically connected to a last stage of the plurality of stages,  
 and the first signal wiring is disposed between the third signal wiring and the driving section.  
   
   
   
       26 . The display device of  claim 25 , wherein the second signal wiring is electrically connected to the third signal wiring.  
   
   
       27 . The display device of  claim 26 , wherein the second signal wiring is formed on a gate insulating layer, the gate insulating layer covering the at least one first signal wiring and the third signal wiring, the second signal wiring electrically connected to the third signal wiring through a contact area formed through the gate insulating layer.  
   
   
       28 . The display device of  claim 26 , wherein the second signal wiring extends substantially parallel to connecting wiring connecting the at least one first signal wiring to the at least two stages of the plurality of stages.  
   
   
       29 . The display device of  claim 26 , wherein the second signal wiring and the third signal wiring transmit a start signal to the first stage and the last stage, respectively.  
   
   
       30 . The display device of  claim 25 , wherein the second signal wiring is electrically insulated from the at least one first signal wiring.  
   
   
       31 . The display device of  claim 25 , further comprising a pad receiving a start signal from an external device.  
   
   
       32 . The display device of  claim 25 , wherein the wiring section comprising: 
 a first pad receiving a start signal from an external device, the first pad extended from the second signal wiring;    a second pad receiving a start signal from an external device, the second pad extended from the third signal wiring; and    a third pad receiving a plurality of signals from an external device, the third pad extended from the first signal wiring, wherein the third pad is disposed between the first pad and the second pad.    
   
   
       33 . The display device of  claim 25 , wherein the second signal wiring applies a start signal activating an operation of the first stage to an input terminal of the first stage, and 
 the third signal wiring applies the start signal to a control terminal of the last stage.    
   
   
       34 . The display device of  claim 25 , wherein the first signal wiring comprises: 
 a first clock wiring transferring a first clock signal to the plurality of stages;    a second clock wiring transferring a second clock signal to the plurality of stages, the second clock signal having opposite phase to the first clock signal; and    an off-voltage wiring providing an off-voltage to the plurality of stages.    
   
   
       35 . The display device of  claim 34 , wherein the first signal wiring further comprises a reset wiring resetting the plurality of stages by providing the plurality of stages with a gate signal outputted from the last stage of the plurality of stages.  
   
   
       36 . The display device of  claim 25 , wherein the array substrate comprises a display area and a peripheral area adjacent to the display area, 
 the display area including a pixel array electrically connected to the plurality of gate lines and the plurality of data lines, the pixel array receiving the gate signal and data signal,    the peripheral area including the gate driver circuit formed on the peripheral area simultaneously through a same process as the pixel array.    
   
   
       37 . The display device of  claim 25 , wherein the array substrate further comprises a repair wiring crossing first and second edge portions of the plurality of data lines, is the repair wiring electrically connected to an opened data line among the plurality of data lines, and, 
 the third signal wiring disposed between a portion of the repair wiring and the first signal wiring.