Metal-oxide-semiconductor device with enhanced source electrode

Abstract

An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.

1 . A method for forming a metal-oxide-semiconductor (MOS) device, comprising the steps of: 
 forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer being of a first conductivity type;    forming first and second source/drain regions of a second conductivity type in the semiconductor layer proximate the gate, the gate being between the first and second source/drain regions;    forming a silicide layer on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate; and    forming at least one insulating layer directly on the silicide layer,    wherein the first source/drain region comprises an n-type region and a p-type region formed adjacent to said n-type region and extending laterally away from said gate, and wherein the silicide layer is formed substantially proximate the n-type and p-type regions such that the silicide layer forms a substantially low-resistance electrical path in parallel with an electrical path formed between the n-type and p-type regions.    
   
   
       2 . The method of  claim 1 , wherein substantially all current associated with the first source/drain region passes through the silicide layer in a direction from the n-type region to a p-type region that is proximate the upper surface of the semiconductor layer.  
   
   
       3 . The method of  claim 1 , wherein the at least one insulating layer comprises at least one conductive layer, the at least one conductive layer being electrically isolated from the silicide layer.  
   
   
       4 . The method of  claim 1 , wherein the silicide layer forms a substantially low-resistance electrical path for conducting current between two or more regions in the semiconductor layer that are electrically isolated from the device.  
   
   
       5 . The method of  claim 1 , further comprising the step of forming a shielding structure proximate the upper surface of the semiconductor layer and between the gate and the second source/drain region, the shielding structure being electrically connected to the first source/drain region, the shielding structure being spaced laterally from the gate and being substantially non-overlapping relative to the gate.  
   
   
       6 . The method of  claim 1 , wherein the first source/drain region comprises a source region and the second source/drain region comprises a drain region.  
   
   
       7 . The method of  claim 1 , wherein the MOS device comprises a diffused MOS (DMOS) device, the first source/drain region comprises a source region and the second source/drain region comprises a drain region.  
   
   
       8 . The method of  claim 7 , wherein the MOS device comprises a lateral DMOS (LDMOS) device.