Vertical MOSFET SRAM cell

Abstract

A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

1 - 19 . (canceled)  
   
   
       20 . A vertical Static Random Access Memory (SRAM) cell device comprising: 
 a pair of pass gate vertical FET transistors (PG 1 ,PG 2 );    a pair of vertical pull-down FET transistors (PD 1 ,PD 2 ) with a first common body (CBN) and a first common source region (S 2 );    a pair of vertical pull-up FET transistors (PU 1 ,PU 2 ) with a second common body (CBP) and a second common source region (S 3 ); and    said FET transistors being connected in an SRAM cell circuit.    
   
   
       21 . A vertical Static Random Access Memory (SRAM) cell device comprising: 
 pass gate FET transistors (PG 1 ,PG 2 );    a pair of vertical pull-down FET transistors (PD 1 ,PD 2 ) with a first common body (CBN) and a first common source region (S 2 );    a pair of vertical pull-up FET transistors (PU 1 ,PU 2 ) with a second common body (CBP) and a second common source region (S 3 );    said FET transistors connected in an SRAM cell circuit; and isolated diffusions formed above said common body comprising isolated drain regions.    
   
   
       22 . A vertical Static Random Access Memory (SRAM) cell device comprising: 
 pass gate FET transistors (PG 1 ,PG 2 );    a pair of vertical pull-down FET transistors (PD 1 ,PD 2 ) with a first common body (CBN) and a first common source region (S 2 );    pair of vertical pull-up FET transistors (PU 1 ,PU 2 ) with a second common body (CBP) and a second common source region (S 3 );    said FET transistors connected in an SRAM cell circuit;    an uppermost common diffusion for an uppermost diffusion for drain regions of an FET;    said uppermost common diffusion formed with a first recess above said first common body and a second recess above said second common body thereby forming isolated diffusions comprising isolated drain regions above each of said first common body and said second common body; and    each said first recess and said second recess being filled with a dielectric material.    
   
   
       23 . The device of  claim 22  wherein said pass gate FET transistors are selected from the group consisting of planar and vertical transistors.  
   
   
       24 . The device of  claim 22  wherein said SRAM device includes dual pairs of pass gate FET transistors forming a dual-port SRAM cell.  
   
   
       25 . The device of  claim 22  including said FET transistors being connected with a sublithographic borderless contact structure formed between said upper diffusion area of non-planar transistor and a zero (M 0 ) metallization layer.  
   
   
       26 . The device of  claim 22  including said FET transistors being connected with a sublithographic borderless contact structure formed between said gate electrode of a non-planar transistor an(d a zero (M 0 ) metallization layer.  
   
   
       27 . The device of  claim 22  including said FET transistors being connected with a sublithographic borderless contact structure formed between said gate electrode of a non-planar transistor and a second metallization layer.  
   
   
       28 . The device of  claim 22  wherein common gate electrodes interconnect pull-down and pull-up vertical FETs.  
   
   
       29 . The device of  claim 22  wherein said gate electrode is made of a heavily doped polycrystalline semiconductor material selected from the group consisting of Si, SiGe, and SiGeC.  
   
   
       30 . The device of  claim 20  including: 
 said first common body region (CBN) being formed above said first common source region (S 2 ); and    said second common body region (CBP) being formed above said second common source region (S 3 ).    
   
   
       31 . The device of  claim 30  including: 
 a first common drain region (D 2 ,D 3 ) formed above said first common body region (CBN); and    a second common drain region (D 4 ,D 5 ) formed above said second common body region (CBP).    
   
   
       32 . The device of  claim 31  including: 
 said first common drain region (D 2 ,D 3 ) being bisected into a first pair of separate drain regions (D 2 ,D 3 );    a first dielectric isolation region (STI) formed between said first pair of separate drain regions (D 2 ,D 3 );    said second common drain region (D 4 ,D 5 ) being bisected into a second pair of separate drain regions (D 4 ,D 5 ); and    a second dielectric isolation region (STI) formed between said second pair of drain regions (D 4 ,D 5 ).    
   
   
       33 . The device of  claim 32  including: 
 said vertical pull-down FET transistors (PD 1 ,PD 2 ) being formed with said first common source region (S 2 ), said first common body region (CBN) and said first separate drain regions (D 2 , D 3 ); and    said vertical pull-up FET transistors (PU 1 ,PU 2 ) being formed with said second common source region (S 3 ), said second common body region (CBP) and said second separate drain regions (D 4 , D 5 ).    
   
   
       34 . The device of  claim 33  including said FET transistors being connected in an SRAM cell circuit.  
   
   
       35 . The device of  claim 20  including: 
 said first common body region (CBN) being formed above said first common source region (S 2 ) and being formed said second common body region (CBP) above said second common source region (S 3 );    first separate pair of drain regions (D 2 ,D 3 ) being formed above said first common body region (CBN); and    a second separate pair of drain regions (D 4 ,D 5  being formed) above said second common body region (CBP); and    said vertical pull-down FET transistors (PD 1 ,PD 2 ) being formed with said first common source region (S 2 ), said first common body region (CBN) and said first separate drain regions (D 2 , D 3 ); and    said vertical pull-up FET transistors (PU 1 ,PU 2 ) being formed with said second common source region (S 3 ), said second common body region (CBP) and said second separate drain regions (D 4 , D 5 ).    
   
   
       36 . The device of  claim 20  including: 
 a set of doped pull-down strata for said pair of vertical pull-down transistors (PD 1 , PD 2 ), comprising a pull-down lower stratum for said first common source region (S 2 ), a pull-down body stratum for said first common body (CBN), and a pull-down upper stratum for a set of pull-down drain regions (D 2 /D 3 );    said upper pull-down stratum and said pull-down lower stratum for said vertical pull-down FET transistors (PD 1 , PD 2 ), having opposite types of dopant from said pull-down body stratum for said first common body (CBN);    a set of doped pull-up strata for said vertical pull-up FET transistors (PU 1 , PU 2 ), comprising a lower pull-up stratum for said second common source region (S 3 ), a pull-up body stratum for said second common body (CBP), and a pull-up upper stratum for a set of pull-up drain regions (D 4 /D 5 );    said pull-up upper stratum and said pull-up lower stratum for said vertical pull-up FET transistors (PU 1 , PU 2 ), having opposite types of dopant from said pull-up body stratum for said second common body (CBP);    a pull-down isolation space bisecting said upper pull-down stratum forming said set of pull-down drain regions (D 2 /D 3 ) for said pull-down FET transistors (PD 1 , PD 2 ), with said pull-down isolation space reaching down to said pull-down body stratum; and    a pull-up isolation space bisecting said upper pull-up stratum forming said pull-up drain regions (D 4 /D 5 ) for said vertical pull-up FET transistors (PU 1 , PU 2 ), with said pull-up isolation space reaching down to said pull-up body stratum.    
   
   
       37 . The device of  claim 36  including said pull-down isolation space and said pull-up isolation space being filled with an isolation dielectric.  
   
   
       38 . The device of  claim 36  wherein said pass gate FET transistors are selected from the group consisting of planar and vertical transistors.  
   
   
       39 . The device of claim  227  wherein said SRAM device includes dual pairs of pass gate FET transistors forming a dual-port SRAM cell.