Dual port memory with asymmetric inputs and outputs, device, system

Abstract

An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a write bus width configured to transfer data from the memory controller to the memory device with the write bus width being different from the read bus width. A memory system including the asymmetric memory interface, memory controller and memory device is disclosed. The asymmetric nature of inputs and outputs reduces pin count by avoiding symmetric replication of bus widths for inputs and outputs.

1 . A memory device interface, comprising: 
 a read data interface of a first bus width;    a write data interface of a second bus width; and    wherein the read data interface and the write data interface transfer data at different data rates.    
   
   
       2 . The memory device interface of  claim 1 , wherein the first bus width is greater in width than the second bus width.  
   
   
       3 . The memory device interface of  claim 1 , wherein at least one of the read data interface and the write data interface is configured to operate according to a multi data rate methodology.  
   
   
       4 . The memory device interface of  claim 1 , wherein the read data interface is configured to operate according to a dual data rate (DDR) methodology.  
   
   
       5 . The memory device interface of  claim 1 , wherein the write data interface is configured to operate according to a dual data rate (DDR) methodology.  
   
   
       6 . The memory device interface of  claim 1 , wherein at least one of the read data interface and the write data interface is configured to operate according to a quad data rate (QDR) methodology.  
   
   
       7 . The memory device interface of  claim 1 , further comprising at least one of a command and address interface configured for coupling with a memory controller.  
   
   
       8 . A memory system, comprising: 
 a memory controller; and    a memory device including a memory device interface, the memory device interface comprising: 
 a read data interface of a first bus width;  
 a write data interface of a second bus width; and  
 wherein the read data interface and the write data interface transfer data at different data rates.  
   
   
   
       9 . The memory system of  claim 8 , wherein the first bus width is greater in width than the second bus width.  
   
   
       10 . The memory system of  claim 8 , wherein the read data interface, the memory controller and the memory device are configured to operate according to a dual data rate (DDR) methodology.  
   
   
       11 . The memory system of  claim 8 , wherein the write data interface, the memory controller and the memory device are configured to operate according to a dual data rate (DDR) methodology.  
   
   
       12 . The memory system of  claim 8 , wherein the memory controller, the memory device and at least one of the read data interface and the write data interface are configured to operate according to a quad data rate (QDR) methodology.  
   
   
       13 . The memory system of  claim 8 , further comprising at least one of a command and address bus coupled between the memory controller and the memory device.  
   
   
       14 . A memory device, comprising: 
 a memory array; and    a memory device interface, comprising: 
 a read data interface of a first bus width;  
 a write data interface of a second bus width; and  
 wherein the read data interface and the write data interface transfer data at different data rates.