Sea-of-fins structure on a semiconductor substrate and method of fabrication

Abstract

A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.

1 . A method of fabricating a semiconductor device, said method comprising: 
 forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation;    forming a nitride spacer around each of said plurality of fin bodies;    forming an isolation region in between each of said fin bodies; and    coating said plurality of fin bodies, said nitride spacers, and the isolation regions with a protective film.    
     
     
         2 . The method of  claim 1 , further comprising: 
 removing said protective film;    forming FinFET devices from a first type of said fin bodies;    forming fin capacitors from a second type of fin bodies; and    forming metal interconnects on said FinFET devices and said fin capacitors.    
     
     
         3 . The method of  claim 2 , wherein formation of each of said FinFET devices comprises: 
 forming a gate conductor over said first type of fin bodies;    forming a channel region below said gate conductor; and    configuring source/drain regions adjacent to said channel region.    
     
     
         4 . The method of  claim 3 , further comprising: 
 exposing said first type of fin bodies by removing said gate conductor from said first type of fin bodies; and    forming a region of semiconductor resistance in the exposed first type of fin bodies.    
     
     
         5 . The method of  claim 3 , further comprising doping a selective portion of said gate conductor to produce a region of semiconductor resistance in said gate conductor.  
     
     
         6 . The method of  claim 2 , further comprising connecting a plurality of said fin capacitors in parallel using a first level of said metal interconnects.  
     
     
         7 . The method of  claim 2 , further comprising: 
 forming a plurality of diodes in said fin bodies; and    connecting said diodes in series.    
     
     
         8 . The method of  claim 1 , further comprising: 
 selectively removing said nitride spacer in selected areas of said semiconductor device adapted to be formed into source/drain regions of said FinFET; and    forming an epitaxial material in said selected areas.    
     
     
         9 . The method of  claim 1 , wherein the fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.  
     
     
         10 . A method of forming a semiconductor device to be used in very large scale integrated circuit (VLSI) applications, said method comprising: 
 forming, on a substrate, an array of fin bodies comprising silicon and adapted to be used in customized fin field effect transistor (FinFET) construction;    forming nitride spacers around each fin body in said array of fin bodies;    separating each said fin body from one another; and    applying a protective film over the array of separated fin bodies.    
     
     
         11 . The method of  claim 10 , further comprising: 
 removing said protective film;    forming FinFET devices from a first type of fin body;    forming fin capacitors from a second type of fin body; and    forming metal interconnects on said FinFET devices and said fin capacitors.    
     
     
         12 . The method of  claim 11 , wherein formation of each of said FinFET devices comprises: 
 forming a gate conductor over said first type of fin body;    forming a channel region below said gate conductor; and    configuring source/drain regions adjacent to said channel region.    
     
     
         13 . The method of  claim 12 , further comprising: 
 exposing said first type of fin body by removing said gate conductor from said first type of fin body; and    forming a region of semiconductor resistance in the exposed first type of fin body.    
     
     
         14 . The method of  claim 12 , further comprising doping a selective portion of said gate conductor to produce a region of semiconductor resistance in said gate conductor.  
     
     
         15 . The method of  claim 11 , further comprising connecting a plurality of said fin capacitors in parallel using a first level of said metal interconnects.  
     
     
         16 . The method of  claim 11 , further comprising: 
 forming a plurality of diodes in said fin body; and    connecting said diodes in series.    
     
     
         17 . The method of  claim 10 , further comprising: 
 selectively removing said nitride spacers in selected areas of said semiconductor device adapted to be formed into source/drain regions of said FinFET; and    forming an epitaxial material in said selected areas.    
     
     
         18 . The method of  claim 10 , wherein the formed semiconductor device is adapted to be used in customized applications as a customized semiconductor device.  
     
     
         19 . A semiconductor device adapted to be used in customized applications as a customized semiconductor device comprising: 
 a substrate;    a plurality of planarized fin bodies on said substrate, wherein the fin bodies are adapted to be used for customized fin field effect transistor (FinFET) device formation;    a nitride spacer around each of said plurality of fin bodies;    an isolation region in between each of said fin bodies; and    a protective film on said plurality of fin bodies, said nitride spacers, and the isolation regions.    
     
     
         20 . The semiconductor device of  claim 19 , wherein said plurality of planarized fin bodies are adapted to be used for any of customized fin resistor, customized fin capacitor, and customized diode device formation.