Reconfigurable circular bus

Abstract

A system provides communication between a plurality of cores in an integrated circuit. The system comprises a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores. An arbiter arbitrates which of the plurality of cores can transmit data at any given time.

1 . A system for providing communication between a plurality of cores in an integrated circuit, they system comprising: 
 a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores; and    arbiter means for arbitrating which of the plurality of cares can transmit data at any given time.    
   
   
       2 . The system of  claim 1  wherein the circular segmented bus comprises a data bus.  
   
   
       3 . The system of  claim 1  wherein the circular segmented bus comprises an address bus.  
   
   
       4 . The system of  claim 1  wherein the circular segmented bus comprises a data bus and an address bus.  
   
   
       5 . The system of  claim 1  wherein the circular segmented bus comprises a transmission gate switch between each pair of adjacent cores.  
   
   
       6 . The system of  claim 4  wherein the circular segmented bus comprises a plurality of multiplexers between each pair of adjacent cores.  
   
   
       7 . The system of  claim 1  wherein the cores are connected in parallel on the circular segmented bus.  
   
   
       8 . An integrated circuit having a reconfigurable bus comprising: 
 a plurality of cores;    a circular bus;    means for operatively connecting the plurality of cores around the circular bus for transferring data on the circular bus between the plurality of cores;    segmenting means operatively positioned in the circular bus for controllably segmenting the circular bus; and    a router operatively connected to the plurality of cores and to the segmenting means for determining which of the plurality of cores can transmit data at any given time and controlling the segmenting means to dynamically segment the circular bus.    
   
   
       9 . The system of  claim 8  wherein the circular bus comprises a data bus.  
   
   
       10 . The system of  claim 8  wherein the circular bus comprises an address bus.  
   
   
       11 . The system of  claim 8  wherein the segmenting means comprises a plurality of transmission gate switches.  
   
   
       12 . The system of  claim 11  wherein the segmenting means comprises a plurality of multiplexers.  
   
   
       13 . The system of  claim 8  wherein the router receives access requests from the cores.  
   
   
       14 . The system of  claim 13  wherein the router dynamically segments the circular segmented bus responsive to the access requests.  
   
   
       15 . The system of  claim 13  wherein the router dynamically segments the circular segmented bus responsive to the access requests and destinations for data and to provide a maximum number of simultaneous transmissions.  
   
   
       16 . The system of  claim 13  wherein the router dynamically segments the circular segmented bus responsive to the access requests and preselect priorities of the access requests.  
   
   
       17 . The system of  claim 8  wherein the plurality of cores comprise bus master circuits and bus slave circuits.  
   
   
       18 . The system of  claim 17  wherein the circular bus comprises a split transaction data bus and address bus.  
   
   
       19 . The system of  claim 18  wherein one of the bus master circuits is operable to request access to the address bus using a request to the arbiter container more significant address bits in an address operation.  
   
   
       20 . The system of  claim 19  wherein a data bus request contains an identification of the one bus master circuit obtained during the address operation.