Semiconductor processing method and field effect transistor
Abstract
A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate. Transistors and transistor gates fabricated according to the above and other methods are disclosed. Further, a transistor includes a semiconductive material and a transistor gate having gate oxide positioned therebetween. A source is formed laterally proximate one of the gate edges and a drain is formed laterally proximate the other of the gate edges. First insulative spacers are formed proximate the gate edges, with the first insulative spacers being doped with at least one of chlorine or fluorine. Second insulative spacers formed over the first insulative spacers.
Claims
exact text as granted — not AI-modified1 . A method of forming a transistor gate comprising:
forming a gate oxide layer over a semiconductive substrate; providing chlorine within the gate oxide layer; and forming a gate proximate the gate oxide layer.
2 . The method of claim 1 wherein the chlorine is provided after forming the gate.
3 . The method of claim 1 wherein the chlorine is provided before forming the gate.
4 . The method of claim 1 wherein the chlorine is provided in the gate oxide layer to a concentration of from about 1×10 19 atoms/cm 3 to about 1×10 21 atoms/cm 3 .
5 . The method of claim 1 wherein the gate comprises opposing lateral edges and a central region therebetween, the chlorine being provided within the gate oxide layer to a greater concentration proximate at least one of the gate edges than in the central region.
6 . A method of forming a transistor gate comprising:
forming a gate and a gate oxide layer in overlapping relation, the gate having opposing edges and a center therebetween; and concentrating at least one of chlorine or fluorine in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center.
7 . The method of claim 6 wherein the concentrating comprises concentrating fluorine.
8 . The method of claim 6 wherein the gate is formed to have a gate width between the edges of 0.25 micron or less, the concentrating forming at least one concentration region in the gate oxide which extends laterally inward from the at least one gate edge no more than about 500 Angstroms.
9 . The method of claim 6 wherein the concentrating comprises diffusion doping.
10 . The method of claim 6 wherein the concentrating comprises ion implanting.
11 . A method of forming a transistor gate comprising:
forming a gate and a gate oxide layer in overlapping relation, the gate having opposing edges and a central region therebetween; and doping the gate oxide layer within the overlap with at least one of chlorine or fluorine proximate the opposing gate edges and leaving the central region substantially undoped with chlorine and fluorine.
12 . The method of claim 11 wherein the doping comprises ion implanting.
13 . The method of claim 11 wherein the doping provides a dopant concentration in the gate oxide layer proximate the edges from about 1×10 19 atoms/cm 3 to about 1×10 21 atoms/cm 3 .
14 . A method of forming a transistor gate comprising the following sequential steps:
forming a gate over a gate oxide layer, the gate having opposing edges; and angle ion implanting at least one of chlorine or fluorine into the gate oxide layer beneath the edges of the gate.
15 . The method of claim 14 wherein the angle is between from about 0.5 degrees to about 10 degrees from perpendicular the gate oxide layer.
16 . The method of claim 14 further comprising annealing the gate oxide layer after the implanting.
17 . A method of forming a transistor gate comprising the following sequential steps:
forming a gate over a gate oxide layer, the gate having opposing lateral edges; and diffusion doping at least one of chlorine or fluorine into the gate oxide layer beneath the gate from laterally outward of the gate edges.
18 . The method of claim 17 wherein the doping provides a dopant concentration in the gate oxide layer proximate the edges from about 1×10 19 atoms/cm 3 to about 1×10 21 atoms/cm 3 .
19 . The method of claim 17 wherein the doping provides a pair of spaced and opposed concentration regions in the gate oxide which extend laterally inward from the gate edges no more than about 500 Angstroms.
20 . The method of claim 17 wherein the doping provides a pair of spaced and opposed concentration regions in the gate oxide which extend laterally inward from the gate edges no more than about 500 Angstroms, the concentration regions having an average dopant concentration in the gate oxide layer proximate the edges from about 1×10 19 atoms/cm 3 to about 1×10 21 atoms/cm 3 .
21 . The method of claim 20 wherein the gate oxide layer between the concentration regions is substantially undoped with chlorine and fluorine.
22 . A method of forming a transistor gate comprising the following steps:
forming a gate over a gate oxide layer, the gate having opposing lateral edges; forming sidewall spacers proximate the opposing lateral edges, the sidewall spacers comprising at least one of chlorine or fluorine; and annealing the spacers at a temperature and for a time period effective to diffuse the fluorine or chlorine from the spacers into the gate oxide layer to beneath the gate.
23 . The method of claim 22 wherein after the annealing, stripping the spacers from the edges.
24 . The method of claim 22 comprising forming the spacers to cover less than all of the lateral edges.
25 . The method of claim 22 comprising forming the spacers to overlie the gate oxide layer.
26 . The method of claim 22 comprising forming the spacers to not overlie any of the gate oxide layer.
27 . The method of claim 22 further comprising:
depositing a layer of insulating material over the gate and the sidewall spacers; and anisotropically etching the layer of insulating material to form spacers over the sidewall spacers.
28 . The method of claim 27 wherein the annealing occurs before the depositing.
29 . The method of claim 27 wherein the annealing occurs after the depositing.
30 . The method of claim 22 further comprising:
providing gate oxide layer material laterally outward of the gate edges; etching only partially into the gate oxide layer laterally outward of the gate edges; and forming said sidewall spacers over the etched gate oxide layer laterally outward of the gate edges.
31 . A transistor comprising:
a semiconductive material and a transistor gate having gate oxide positioned therebetween, the gate having opposing gate edges and a central region therebetween; a source formed laterally proximate one of the gate edges and a drain formed laterally proximate the other of the gate edges; and chlorine within the gate oxide layer between the semiconductive material and the transistor gate.
32 . The transistor of claim 31 wherein the chlorine is provided in the gate oxide layer to a concentration of from about 1×10 19 atoms/cm 3 to about 1×10 21 atoms/cm 3 .
33 . The transistor of claim 31 wherein the chlorine is provided within the gate oxide layer to a greater concentration proximate at least one of the gate edges than in the central region.
34 . The transistor of claim 31 wherein the chlorine is provided within the gate oxide layer to a greater concentration proximate the other gate edge than in the central region.
35 . The transistor of claim 31 wherein the chlorine is provided within the gate oxide layer to a greater concentration proximate both gate edges than in the central region.
36 . The transistor of claim 31 wherein the central region is substantially void of chlorine.
37 . A transistor comprising:
a semiconductive material and a transistor gate having gate oxide positioned therebetween, the gate having opposing gate edges and a central region therebetween; a source formed laterally proximate one of the gate edges and a drain formed laterally proximate the other of the gate edges; and at least one of fluorine or chlorine being concentrated in the gate oxide layer between the semiconductive material and the transistor gate more proximate at least one of the gate edges than the central region.
38 . The transistor of claim 37 wherein fluorine is concentrated.
39 . The transistor of claim 37 wherein chlorine is concentrated.
40 . The transistor of claim 37 wherein the central region of the gate oxide layer is substantially void of chlorine and fluorine.
41 . The transistor of claim 37 wherein the concentrated chlorine or fluorine is provided in the gate oxide layer to a concentration of from about 1×10 19 atoms/cm 3 to about 1×10 21 atoms/cm 3 .
42 . The transistor of claim 37 wherein the concentrated chlorine or fluorine is provided in the gate oxide layer to a concentration of from about 1×10 19 atoms/cm 3 to about 1×10 21 atoms/cm 3 , and wherein the central region of the gate oxide layer is substantially void of chlorine and fluorine.
43 . The transistor of claim 37 wherein the at least one of fluorine or chlorine is concentrated in the gate oxide layer more proximate both gate edges than in the central region.
44 . The transistor of claim 37 wherein the at least one of fluorine or chlorine is concentrated in the gate oxide layer more proximate at least the other gate edge.
45 . The transistor of claim 37 wherein the gate is formed to have a gate width between the edges of 0.25 micron or less, the concentrated at least one of fluorine or chlorine extending laterally inward from the at least one gate edge no more than about 500 Angstroms.
46 . The transistor of claim 37 wherein the gate is formed to have a gate width between the edges of 0.25 micron or less, the concentrated at least one of fluorine or chlorine extending laterally inward from the at least one gate edge no more than about 500 Angstroms with an average concentration of from about 1×10 19 atoms/cm 3 to about 1×10 21 atoms/cm 3 .
47 . A transistor comprising:
a semiconductive material and a transistor gate having gate oxide positioned therebetween, the gate having opposing gate edges; a source formed laterally proximate one of the gate edges and a drain formed laterally proximate the other of the gate edges; first insulative spacers formed proximate the gate edges, the first insulative spacers being doped with at least one of chlorine or fluorine; and second insulative spacers formed over the first insulative spacers.
48 . The transistor of claim 47 wherein the second insulative spacers at least as initially provided are substantially undoped with either chlorine or fluorine.
49 . The transistor of claim 47 further comprising at least one of chlorine or fluorine within the gate oxide layer proximate the gate edges.
50 . The transistor of claim 47 wherein the gate oxide layer includes a central region between the opposing gate edges, and further comprising at least one of chlorine or fluorine within the gate oxide layer proximate the gate edges, the central region being substantially void of chlorine and fluorine.Cited by (0)
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