Fabricating sub-lithographic contacts

Abstract

A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing to be overcome to provide reduced critical dimension elements.

1 . A method comprising: 
 forming a first sidewall spacer within a pore; and    forming a second sidewall spacer within said pore over the first sidewall spacer.    
   
   
       2 . The method of  claim 1  including anisotropically etching a spacer material to form said first sidewall spacer.  
   
   
       3 . The method of  claim 2  including forming a bread loaf portion in said spacer material and reducing the extent of said bread loaf portion by etching.  
   
   
       4 . The method of  claim 1  including forming said first sidewall spacer of nitride.  
   
   
       5 . The method of  claim 1  including forming said second sidewall spacer by depositing a second material over said first sidewall spacer and anisotropically etching said second material.  
   
   
       6 . The method of  claim 5  including forming a bread loaf portion on said second material and etching to reduce the extent of said bread loaf portion.  
   
   
       7 . The method of  claim 1  including anisotropically etching to form said first sidewall spacer before forming said second sidewall spacer.  
   
   
       8 . The method of  claim 1  including forming a heater in said pore after forming said first and second sidewall spacers and forming a chalcogenide layer over said heater.  
   
   
       9 . The method of  claim 1  including forming said pore with a sub-lithographic dimension after forming said first and second sidewall spacers.  
   
   
       10 . The method of  claim 9  including forming said pore with a dimension of about 60 nanometers or less.  
   
   
       11 . A semiconductor structure comprising: 
 an insulating layer;    a pore formed in said insulating layer; and    a pair of sidewall spacers formed on top of one another within said pore.    
   
   
       12 . The structure of  claim 11  wherein said sidewall spacers are separated by a sub-lithographic distance.  
   
   
       13 . The structure of  claim 12  wherein said distance is about 60 nanometers or less.  
   
   
       14 . The structure of  claim 11  including a heater in said pore and a chalcogenide layer over said heater.  
   
   
       15 . The structure of  claim 11  including a conductor under said pore, and said pore is open through said sidewall spacers down to said conductor.  
   
   
       16 . A method comprising: 
 forming a first and second sidewall spacer one over the other within a pore;    forming a heater within said pore; and    forming a chalcogenide layer over said heater.    
   
   
       17 . The method of  claim 16  including forming the first sidewall spacer within said pore by anisotropically etching a first spacer material.  
   
   
       18 . The method of  claim 17  including forming a bread loaf portion in said first spacer material and reducing the extent of said bread loaf portion by etching.  
   
   
       19 . The method of  claim 18  including depositing a second spacer material to form said second sidewall spacer, said second spacer material including a bread loaf portion and etching to reduce the extent of said bread loaf portion.  
   
   
       20 . A phase change memory comprising: 
 an insulating layer;    a pore formed in said insulating layer;    a first and second sidewall spacer formed on top of one another within said pore;    a heater formed within said pore; and    a chalcogenide material over said heater.    
   
   
       21 . The memory of  claim 20  wherein said pore opening is reduced to a sub-lithographic dimension by said spacers.  
   
   
       22 . The memory of  claim 21  wherein said pore is reduced to 60 nanometers or less by said spacers.  
   
   
       23 . The memory of  claim 20  including a conductor, under said insulating layer, said heater electrically coupled to said conductor.  
   
   
       24 . A system comprising: 
 a controller;    a battery coupled to said controller; and    a memory coupled to said controller, said memory including an insulating layer, a pore formed in said insulating layer, first and second sidewall spacers formed within said pore, a heater formed within said pore, and a chalcogenide material over said heater.    
   
   
       25 . The system of  claim 24  wherein said heater has a dimension that is sub-lithographic.  
   
   
       26 . The system of  claim 25  wherein said heater has a dimension less than 60 nanometers.  
   
   
       27 . The system of  claim 26  wherein the width of said heater is less than or equal to 60 nanometers.