Semiconductor Memory Device and Method of Operating the Same
Abstract
A semiconductor memory device includes semiconductor memory cells with at least one memory cell capable of acting either in a first mode, wherein it functions as a storage device for ECC information, or in a second mode, wherein it functions as either as a redundant memory cell or a as a cell storing ordinary information. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either in the first mode or in the second mode. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either in the first mode or in either of the selected second modes.
Claims
exact text as granted — not AI-modified1 . A semiconductor memory device comprising;
a plurality of semiconductor memory cells including at least one memory cell capable of operating in a first mode, in which the at least one memory cell functions as a storage device for Error Correction Code information, and in a second mode, in which the at least one memory cell functions as a storage device for information being different from Error Correction Code information; and a signal control device operable to signal that the at least one memory cell is to operate in the first mode or in the second mode.
2 . The semiconductor memory device of claim 1 , wherein in said second mode the at least one memory cell functions as a redundant memory cell.
3 . The semiconductor memory device of claim 1 , wherein in said second mode the at least one memory cell functions as a memory cell for storing ordinary information.
4 . The semiconductor memory device of claim 1 , wherein the semiconductor memory device is a semiconductor memory component comprising the signal control device.
5 . The semiconductor memory device of claim 1 further comprising a plurality of semiconductor memory components.
6 . The semiconductor memory device of claim 5 , wherein the signal control device is common to each of the semiconductor memory components.
7 . The semiconductor memory device of claim 1 , wherein the signal control device is a fuse.
8 . The semiconductor memory device of claim 1 , wherein the signal control device is a reprogrammable signal control device.
9 . The semiconductor memory device of claim 1 , wherein a status of the signal control device can be determined by a technical device.
10 . The semiconductor memory device of claim 2 further comprising a redundancy device operable to replace a defective memory cell when the at least one memory cell operates in the second mode as a redundant memory cell.
11 . A method of operating the semiconductor memory device of claim 1 , the method comprising the steps of: registering a status of the signal control device and, depending on the status of the signal device, either operating the at least one memory cell in the first mode, in which it acts as a storage device for ECC information, or operating the at least one memory cell in the second mode.
12 . A semiconductor memory device comprising;
a plurality of semiconductor memory cells including at least one memory cell capable of operating in a first mode, in which the at least one memory cell functions as a storage device for Error Correction Code information, and in a second mode, in which the at least one memory cell functions as either as a redundant memory cell or as a memory cell for storing ordinary information; and a signal control device operable to signal that the at least one memory cell is to operate in the first mode or in the second mode.
13 . The semiconductor memory device of claim 1 , wherein, in the second mode, the at least one memory cell functions as a redundant memory cell.
14 . The semiconductor memory device of claim 1 , wherein, in the second mode, the at least one memory cell functions as a memory cell for storing ordinary information.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.