Method of programming a four-level flash memory device and a related page buffer

Abstract

A four-level FLASH memory device includes an array of singularly addressable preliminarily erased memory cells, with each memory cell capable of storing a two-bit datum. When the threshold voltage of a memory cell is verified to have reached the desired distribution, the cell is read using a test read voltage smaller than or equal to the program voltage. In this situation the voltage V<SUB>S </SUB>on the source node is negligible, and the programmed state of the cell may be correctly verified.

1 . A method of programming a four-level FLASH memory device including an array of singularly addressable preliminarily erased memory cells, each capable of storing a two-bit datum, by programming first the least significant bit in all the cells and then the most significant bit in all the cells, comprising the following steps: 
 a) applying program pulses in parallel to all the cells in which a least significant bit of a certain logic value (0) must be stored, increasing stepwise the threshold voltage up to make it surpass a first program voltage (VVFY 1 ), and leaving in the erased state the other cells in which a least significant bit of opposite logic value (1) must be stored,    b) applying program pulses in parallel to all the cells in which a least significant bit of said certain logic value (0) must be stored, increasing stepwise the threshold voltage up to make it surpass a second program voltage (VVFY 2 ) to all the cells in which the least significant bit equals said certain logic value (0), or a third program voltage (VVFY 3 ) to all the cells in which the least significant bit differs from said certain logic value, and leaving all the cells, in which a most significant bit of opposite logic value (1) must be stored, as they are at the end of step a),    characterized in that the method comprises performing after step a) the following additional steps before step b):    a1) testing the least significant bit programming by reading the array cells using a first test read voltage (VVFY 1 -Δ ) smaller than or equal to said first program voltage (VVFY 1 );    a2) if any cell fails the test, applying program pulses in parallel to all the failed cells increasing stepwise their threshold voltage up to make it surpass said first program voltage (VVFY 1 ).    
     
     
         2 . The method of  claim 1 , further comprising performing after step b) the following additional steps: 
 b1) testing the most significant bit programming carried out in step b) by reading the array cells either using a second test read voltage (VVFY 2 -Δ ) or a third test read voltage (VVFY 3 -Δ ), respectively, said second and third test read voltages (VVFY 2 -Δ , VVFY 3 -Δ ) being smaller than or equal to said second program voltage (VVFY 2 ) or third program voltage (VVFY 3 ), respectively;    b2) if any cell fails the test, applying program pulses in parallel to all the failed cells increasing stepwise their threshold voltage up to make it surpass the second program voltage (VVFY 2 ) or the third program voltage (VVFY 3 ), respectively.    
     
     
         3 . The method of  claim 1 , wherein said FLASH memory comprises a page buffer including at least a first latch (LSB LATCH) and a second latch (MSB LATCH) for each memory cell for temporarily storing the least significant bit and the most significant bit, respectively, wherein said step a) is carried out through the following operations: 
 aa) loading in both said latches the least significant bit of a two-bit string to be written in the memory cell,    ab) applying program pulses in parallel to all the cells in which the bit stored in the respective first latch (LSB LATCH) equals said certain logic value (0), increasing step by step the threshold voltage of all the cells to be programmed up to make it surpass said first program voltage (VVFY 1 ), and leaving in the erased state the other cells,    ac) as soon as the threshold voltage of each cell surpasses said first program voltage (VVFY 1 ), loading the inverse of said certain logic value (1) in the respective first latch (LSB LATCH);    wherein step a1) is carried out through the following operations:    a1a) copying the value stored in each of said second latches (MSB LATCH) in the corresponding first latch (LSB LATCH),    a1b) testing the least significant bit programming by reading the array cells the respective first latch (LSB LATCH) of which stores a bit of said certain logic value (0) using said first test read voltage (VVFY 1 -Δ ), and loading the inverse of said certain logic value (1) in the first latch (LSB LATCH) if said test is verified;    wherein step a2) is carried out through the following operations:    a2a) applying program pulses in parallel to all the cells the first latch (LSB LATCH) of which stores said certain logic value (0),    a2b) as soon as the threshold voltage of each cell surpasses said first program voltage (VVFY 1 ), loading the inverse of said certain logic value (1) in the respective first latch (LSB LATCH).    
     
     
         4 . The method of  claim 2 , wherein said page buffer comprises an auxiliary latch (THIRD LATCH) for each memory cell, said step b) being carried out through the following operations: 
 ba) reading the array cells using a first read voltage (Vread 0 ) for discriminating programmed cells from erased cells and loading in said first latch (LSB LATCH) a bit of said certain logic value (0) or its inverse (1), respectively,    bb) loading in said second latches (MSB LATCH) the respective most significant bits,    bc) copying in said auxiliary latches (THIRD LATCH) the bits stored in the respective first latch (LSB LATCH),    bd) applying program pulses in parallel to all the cells the second latch (MSB LATCH) of which stores said certain logic value (0), by increasing stepwise the threshold voltage of all the cells the first latch (LSB LATCH) of which stores said certain logic value (0) up to make it surpass the second program voltage (VVFY 2 ) or of all the cells the first latch (LSB LATCH) of which stores the inverse logic value (1) up to make it surpass the third program voltage (VVFY 3 ),    be) as soon as the threshold voltage of each cell surpasses said second (VVFY 2 ) or third program voltage (VVFY 3 ), respectively, loading said inverse logic value (1) in the respective first latch (LSB LATCH) and in the second latch (MSB LATCH);    wherein step b1) is carried out through the following operations:    b1a) copying the value stored in said auxiliary latches (THIRD LATCH) in the corresponding first latches (LSB LATCH),    b1b) reading the array cells using a second read voltage (Vread 1 ) smaller than said second program voltage (VVFY 2 ) and loading in said second latches (MSB LATCH) the most significant bits that have been read,    b1c) testing the most significant bit programming by reading the array cells the second latch (MSB LATCH) of which stores said certain logic value (0) using a second test read voltage (VVFY 2 -Δ ) if the least significant latch (LSB LATCH) stores said certain logic value (0) or a third test read voltage (VVFY 3 -Δ ) if the least significant latch (LSB LATCH) stores said inverse logic value (1), smaller than or equal to said second program voltage (VVFY 2 ) or third program voltage (VVFY 3 ), respectively, and loading said inverse logic value (1) in the second latch (MSB LATCH) and in the first latch (LSB LATCH) if the read most significant bit equals said certain logic value (0);    wherein step b2) is carried out through the following operations:    b2a) applying program pulses in parallel to all the cells the second latch (MSB LATCH) of which and the first latch (LSB LATCH) of which store said inverse logic value (1),    b2b) as soon as the threshold voltage of each cell surpasses said second program voltage (VVFY 2 ) or third program voltage (VVFY 3 ), loading said inverse logic value (1) in the second latch (MSB LATCH) and in the first latch (LSB LATCH).    
     
     
         5 . The method of  claim 2 , wherein said page buffer comprises an auxiliary latch (THIRD LATCH) for each memory cell, the auxiliary latch (THIRD LATCH) being used for carrying out steps aa) to a2b) instead of the second latch (MSB LATCH), said step b) being carried out through the following operations: 
 ba) loading in said auxiliary latch (THIRD LATCH) the most significant bit of the two-bit string to be stored therein,    bb) copying in second latch (MSB LATCH) the bit stored in said auxiliary latch (THIRD LATCH),    bc) reading the array cells using a first read voltage (Vread 0 ) for discriminating programmed cells from erased cells and loading in said first latch (LSB LATCH) a bit of said certain logic value (0) or its inverse (1), respectively,    bd) applying program pulses in parallel to all the cells the second latch (MSB LATCH) of which stores said certain logic value (0), by increasing stepwise the threshold voltage of all the cells the first latch (LSB LATCH) of which stores said certain logic value (0) up to make it surpass the second program voltage (VVFY 2 ) or of all the cells the first latch (LSB LATCH) of which stores the inverse logic value (1) up to make it surpass the third program voltage (VVFY 3 ),    be) as soon as the threshold voltage of each cell surpasses said second (VVFY 2 ) or third program voltage (VVFY 3 ), respectively, loading said inverse logic value (1) in the respective first latch (LSB LATCH) and in the second latch (MSB LATCH);    wherein step b1) is carried out through the following operations:    b1a) copying the value stored in said auxiliary latches (THIRD LATCH) in the corresponding second latches (MSB LATCH),    b1b) reading the array cells using a first read voltage (Vread 0 ) or a third read voltage (Vread 2 ), that are smaller than said first program voltage (VVFY 1 ) or said third program voltage (VVFY 3 ), respectively, and loading in said first latches (LSB LATCH) the least significant bits that have been read,    b1c) testing the most significant bit programming by reading the array cells the second latch (MSB LATCH) of which stores said certain logic value (0) using a second test read voltage (VVFY 2 -Δ ) if the least significant latch (LSB LATCH) stores said certain logic value (0) or a third test read voltage (VVFY 3 -Δ ) if the least significant latch (LSB LATCH) stores said inverse logic value (1), smaller than or equal to said second program voltage (VVFY 2 ) or third program voltage (VVFY 3 ), respectively, and loading said inverse logic value (1) in the second latch (MSB LATCH) and in the first latch (LSB LATCH) if the read most significant bit equals said certain logic value (0);    wherein step b2) is carried out through the following operations:    b2a) applying program pulses in parallel to all the cells the second latch (MSB LATCH) of which and the first latch (LSB LATCH) of which store said inverse logic value (1),    b2b) as soon as the threshold voltage of each cell surpasses said second program voltage (VVFY 2 ) or third program voltage (VVFY 3 ), loading said inverse logic value (1) in the second latch (MSB LATCH) and in the first latch (LSB LATCH).    
     
     
         6 . The method of  claim 2 , wherein said step b) is carried out through the following operations: 
 ba) loading in said second latches (MSB LATCH) the respective most significant bits,    bb) reading the array cells using a first read voltage (Vread 0 ) for discriminating programmed cells from erased cells and loading in said first latch (LSB LATCH) a bit of said certain logic value (0) or its inverse (1), respectively,    bc) applying program pulses in parallel to all the cells the second latch (MSB LATCH) of which stores said certain logic value (0), by increasing stepwise the threshold voltage of all the cells the first latch (LSB LATCH) of which stores said certain logic value (0) up to make it surpass the second program voltage (VVFY 2 ) or of all the cells the first latch (LSB LATCH) of which stores the inverse logic value (1) up to make it surpass the third program voltage (VVFY 3 ),    bd) as soon as the threshold voltage of each cell surpasses said second (VVFY 2 ) or third program voltage (VVFY 3 ), respectively, loading said inverse logic value (1) in the respective first latch (LSB LATCH) and in the second latch (MSB LATCH);    wherein step b1) is carried out through the following operations:    b1a) reading the array cells using a second read voltage (Vread 1 ) smaller than said second program voltage (VVFY 2 ) and loading in said second latches (MSB LATCH) the most significant bits that have been read,    b1b) reading the array cells using a first read voltage (Vread 0 ) or a third read voltage (Vread 2 ), that are smaller than said first program voltage (VVFY 1 ) or said third program voltage (VVFY 3 ), respectively, and loading in said first latches (LSB LATCH) the least significant bits that have been read,    b1c) testing the most significant bit programming by reading the array cells the second latch (MSB LATCH) of which stores said certain logic value (0) using a second test read voltage (VVFY 2 -Δ ) if the least significant latch (LSB LATCH) stores said certain logic value (0) or a third test read voltage (VVFY 3 -Δ ) if the least significant latch (LSB LATCH) stores said inverse logic value (1), smaller than or equal to said second program voltage (VVFY 2 ) or third program voltage (VVFY 3 ), respectively, and loading said inverse logic value (1) in the second latch (MSB LATCH) and in the first latch (LSB LATCH) if the read most significant bit equals said certain logic value (0);    wherein step b2) is carried out through the following operations:    b2a) applying program pulses in parallel to all the cells the second latch (MSB LATCH) of which and the first latch (LSB LATCH) of which store said inverse logic value (1),    b2b) as soon as the threshold voltage of each cell surpasses said second program voltage (VVFY 2 ) or third program voltage (VVFY 3 ), loading said inverse logic value (1) in the second latch (MSB LATCH) and in the first latch (LSB LATCH).    
     
     
         7 . A page buffer for a four-level FLASH memory device including an array of singularly addressable preliminarily erased memory cells, each capable of storing a two-bit datum, said FLASH memory comprising a page buffer including at least a first latch (LSB LATCH) and a second latch (MSB LATCH) for each memory cell for temporarily storing the least significant bit and the most significant bit, respectively, characterized in that it comprises 
 an auxiliary latch (THIRD LATCH) for each memory cell;    controlled circuit means for coupling the auxiliary latch (THIRD LATCH) to said first latch (LSB LATCH) or to said second latch (MSB LATCH) for implementing the method of  claim 4 , respectively.