Systems and methods for selectively inclusive cache

Abstract

Embodiments include systems and methods for selectively inclusive multi-level cache. When data for which memory coherency is designated is received from a process and stored into a lower level cache the data is copied into a higher level of cache. When the data is snooped it is snooped from the higher level cache and not the lower level of cache. When data is invalidated in the higher level cache, the data is invalidated in the lower level cache also. Lines of higher level cache are inclusive of lower level cache lines for data for which memory coherency is designated, but need not be inclusive of data for which coherency is not designated.

1 . A multi-level cache system, comprising: 
 at least a lower level cache memory and a higher level cache memory;    a coherency determiner to determine from a predefined attribute if coherency is designated for an item of data in the lower level cache; and    a cache controller to copy the item of data from the lower level cache to the higher level cache if coherency is designated for the item of data.    
     
     
         2 . The system of  claim 1 , further comprising a validity checker to determine in response to a snoop request whether the data copied to higher level cache for which coherency is designated is held in a modified state.  
     
     
         3 . The system of  claim 1 , further comprising an invalidation controller to invalidate an item of data in the lower level cache in response to an invalidation signal from the higher level cache.  
     
     
         4 . The system of  claim 2 , wherein the invalidation signal from the higher level cache is generated in response to an invalidation signal from a snoop interface.  
     
     
         5 . The system of  claim 1 , wherein the cache controller comprises a write-through controller to determine from an attribute of the data whether the item of data is designated as write-through, and if so, then copying the data from the lower level cache to the higher level cache.  
     
     
         6 . The system of  claim 5 , wherein the write-through attribute is true if the predefined attribute is true.  
     
     
         7 . The system of  claim 1 , wherein in response to a snoop request the system detects whether data is held in modified state in a highest level of cache without determining whether a lower level of cache holds the data in modified state.  
     
     
         8 . The system of  claim 1 , wherein the predefined attribute includes memory coherency  
     
     
         9 . A multi-level cache system, comprising: 
 a plurality of processors, a processor comprising execution units and a lower level of cache and a higher level of cache;    a system memory commonly shared by a plurality of the processors;    a processor local bus comprising circuitry to enable transfer of data between a plurality of the processors and the system memory;    a coherency determiner to determine whether coherency is designated for an item of data stored in the lower level of cache;    a cache control mechanism to copy an item of data from the lower level of cache to the higher level of cache if memory coherency is designated for the item of data and to bypass the step of copying the item of data from the lower level cache to the higher level cache if memory coherency is not designated for the item of data;    
     
     
         10 . The system of  claim 9 , further comprising a validity checking mechanism to determine in response to a snoop request whether requested data is held in a modified state in a highest level of cache.  
     
     
         11 . The system of  claim 9 , further comprising a validation control mechanism to invalidate data in the lower level cache in response to a signal from a control mechanism of the higher level cache.  
     
     
         12 . The system of  claim 9 , further comprising a master interface to facilitate transfer of data between the system memory and a plurality of processors.  
     
     
         13 . The system of  claim 9 , wherein the processor local bus comprises a snoop interface to broadcast a snoop request to a plurality of snoopable processors.  
     
     
         14 . The system of  claim 9 , wherein the cache control mechanism comprises circuitry to invalidate data in the lower level cache in response to an invalidation of the data copied into the higher level cache.  
     
     
         15 . The system of  claim 9 , wherein the cache control mechanism responds to a snoop request for an item of data by determining if the requested item of data is held in a modified state in a highest level of cache without determining if the data is in a lower level cache.  
     
     
         16 . The system of  claim 9 , wherein the cache control mechanism is adapted to invalidate data in the lower level cache in response to an invalidation signal from a control mechanism of the higher level cache.  
     
     
         17 . A method for allocating memory in a multi-level-cache system, comprising: 
 determining from a user-specified attribute associated with an item of data in a first, lower level of cache that memory coherency is designated for the item of data;    copying the item of data from the first cache to a second, higher level of cache if memory coherency is designated for the item of data; and    bypassing a step of copying the item of data from the first cache to the second cache if memory coherency is not designated for the item of data.    
     
     
         18 . The method of  claim 16 , further comprising: 
 detecting a condition wherein the item of data copied to the higher level cache is invalid; and    invalidating the item of data in the first, lower level of cache; in response to the detected condition.    
     
     
         19 . The method of  claim 17 , further comprising detecting a snoop request and limiting the snoop request to a request for modified data from the higher level of cache without snooping the lower level of cache.  
     
     
         20 . The method of  claim 16 , further comprising inspecting a highest level of cache in a hierarchy of cache in response to a snoop request for the item of data for which memory coherency is designated but omitting a step of inspecting a lower level of cache in response to the snoop request.  
     
     
         21 . The method of  claim 16 , further comprising invalidating data in the lower level cache if the copied data in the higher level cache is invalidated.