Method for testing semiconductor devices and an apparatus therefor

Abstract

A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.

1 . A process for integrated circuit device fabrication comprising: 
 introducing an integrated circuit device into an apparatus for testing;    providing a first test station where integrated circuit devices are tested individually;    populating a test board with a plurality of sockets;    providing a second test station where devices are tested while populated in said test board; and    electing to perform an electrical test on an integrated circuit device at one of either said first test station, said second test station or both.    
   
   
       2 . The process of  claim 1  further comprising: 
 moving said populated test board from a first position proximate to said first test station to a second position proximate said second test station;    populating said test board with said integrated circuit devices when said test board is in said first position and;    performing the electrical test at said second position while said devices are in said test board.    
   
   
       3 . The process of  claim 1  wherein, after electing to perform said electrical test on said integrated circuit device at said first station, the process further comprises: 
 determining whether the device passes or fails said electrical test and populating said test boards only with integrated circuit devices that pass said electrical test at said first station.    
   
   
       4 . The process of  claim 3  further comprising: 
 submitting a query to a database containing results of prior electrical tests when populating said test boards with said integrated circuit devices, said results identified in the data base by the particular socket in the particular test board associated with said electrical test, said query identifying the particular socket in the particular circuit board for which the query is made;    receiving a response to said query; and    deciding to populate said socket with said integrated circuit device based on said response to said query.    
   
   
       5 . The process of  claim 4  wherein said integrated circuit is not populated into said socket if said response to said query indicates said socket failed a previous electrical test.  
   
   
       6 . The process of  claim 4  wherein said integrated circuit is not populated into said socket if said response to said query indicates that a known good integrated circuit failed an electrical test when in said socket.  
   
   
       7 . The process of  claim 4  wherein said integrated circuit is used to populate said socket if said response to said query indicates that said socket is good.  
   
   
       8 . A process for integrated circuit device fabrication comprising: 
 introducing an integrated circuit device into an apparatus for testing;    providing a first test station that subjects individual integrated circuits to an electrical test;    populating a socket in a test board having a plurality of sockets with said integrated circuit device whether or not said devices fail said first test;    removing devices that failed said test from said test board;    populating sockets from which failed devices were removed with devices that passed said first test; and    providing a parallel test station where devices are tested while populated in said test board.