Alpha particle shields in chip packaging

Abstract

A structure and a method for forming the same. The structure includes an integrated circuit comprising N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit. The structure further includes N solder bumps corresponding to the N chip electric pads. A semiconductor interposing shield is sandwiched between the integrated circuit and the N solder bumps. The structure further includes N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.

1 . A structure, comprising: 
 (a) an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit;    (b) N solder bumps corresponding to the N chip electric pads;    (c) a semiconductor interposing shield sandwiched between the integrated circuit and the N solder bumps; and    (d) N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads.    
     
     
         2 . The structure of  claim 1 , wherein the semiconductor interposing shield has a thickness of at least 50 μm.  
     
     
         3 . The structure of  claim 1 , wherein the semiconductor interposing shield has a thickness sufficiently large such that at least a pre-specified percentage of alpha particles entering the semiconductor interposing shield do not pass through the semiconductor interposing shield.  
     
     
         4 . The structure of  claim 3 , wherein the semiconductor interposing shield comprises metal regions embedded in the semiconductor interposing shield, wherein the metal regions are electrically insulated from the N electric conductors.  
     
     
         5 . The structure of  claim 1 , wherein the N electric conductors are electrically insulated from the semiconductor interposing shield.  
     
     
         6 . The structure of  claim 1 , wherein each conductor of the N electric conductors has an annular shape.  
     
     
         7 . The structure of  claim 1 , further comprising a ceramic substrate including N substrate pads, wherein the N solder bumps are bonded to the N substrate pads.  
     
     
         8 . A structure, comprising: 
 (a) an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit;    (b) N solder bumps corresponding to the N chip electric pads;    (c) a semiconductor interposing shield sandwiched between the integrated circuit and the N solder bumps, wherein the semiconductor interposing shield has a thickness of at least 50 μm;    (d) N electric conductors (i) passing through the semiconductor interposing shield and (ii) electrically connecting the N solder bumps to the N chip electric pads; and    (e) a ceramic substrate including N substrate pads, wherein the N solder bumps are bonded to the N substrate pads.    
     
     
         9 . The structure of  claim 8 , wherein the semiconductor interposing shield has a thickness sufficiently large such that at least a pre-specified percentage of alpha particles entering the semiconductor interposing shield from the ceramic substrate do not pass through the semiconductor interposing shield to reach the integrated circuit.  
     
     
         10 . The structure of  claim 8 , wherein the semiconductor interposing shield comprises boron dopants.  
     
     
         11 . The structure of  claim 8 , further comprising a metal layer sandwiched between and electrically insulated from the semiconductor interposing shield and the N solder bumps.  
     
     
         12 . The structure of  claim 11 , wherein the metal layer has a thickness of less than 15 cm, and wherein the semiconductor interposing shield has a thickness in a range of 30 μm-70 μm.  
     
     
         13 . The structure of  claim 11 , wherein the metal layer has a thickness in a range of 10 μm-15 μm, and wherein the semiconductor interposing shield has a thickness of less than 1 μm.  
     
     
         14 . A structure fabrication method, comprising: 
 providing an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit;    providing an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom side;    bonding the integrated circuit to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors;    polishing the bottom side of the interposing shield so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield after said bonding the integrated circuit to the top side is performed; and    forming N solder bumps on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors.    
     
     
         15 . The method of  claim 14 , further comprising, after said forming the N solder bumps is performed, bonding a ceramic substrate that includes N substrate pads such that the N substrate pads are bonded to the N solder bumps.  
     
     
         16 . The structure of  claim 14 , wherein the interposing shield comprises essentially only a semiconductor material.  
     
     
         17 . The structure of  claim 16 , wherein the interposing shield has a thickness of at least 50 μm after said polishing the bottom side is performed.  
     
     
         18 . The method of  claim 14 , wherein said providing the interposing shield comprises: 
 providing a semiconductor layer;    creating N trenches in the semiconductor layer;    filling the N trenches with an electrically conducting material so as to form the N electric conductors, wherein the semiconductor layer, after said filling the N trenches is performed, comprises the interposing shield.    
     
     
         19 . The method of  claim 18 , wherein said providing the interposing shield further comprises forming a dielectric layer on side walls of the N trenches before said filling the N trenches is performed.  
     
     
         20 . The method of  claim 18 , wherein each trench of the N trenches has an annular shape.  
     
     
         21 . A structure fabrication method, comprising: 
 providing an integrated circuit including N chip electric pads, wherein N is a positive integer, and wherein the N chip electric pads are electrically connected to a plurality of devices on the integrated circuit;    providing a semiconductor interposing shield having a top side and a bottom side and having N electric conductors in the semiconductor shield, wherein the N electric conductors are exposed to a surrounding ambient at the top side but not being exposed to the surrounding ambient at the bottom side;    bonding the integrated circuit to the top side of the semiconductor interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors;    polishing the bottom side of the semiconductor interposing shield so as to expose the N electric conductors to the surrounding ambient at the bottom side of the semiconductor interposing shield after said bonding the integrated circuit to the top side is performed;    forming N solder bumps on the polished bottom side of the semiconductor interposing shield and in electrical contact with the N electric conductors; and    after said forming the N solder bumps is performed, bonding a ceramic substrate that includes N substrate pads such that the N substrate pads are bonded to the N solder bumps,    wherein the semiconductor interposing shield comprises essentially only silicon, and    wherein the semiconductor interposing shield has a thickness of at least 50 μm after said polishing the bottom side is performed.    
     
     
         22 . The method of  claim 21 , wherein said providing the semiconductor interposing shield comprises: 
 providing a semiconductor layer;    creating N trenches in the semiconductor layer;    filling the N trenches with an electrically conducting material so as to form the N electric conductors, wherein the semiconductor layer, after said filling the N trenches is performed, comprises the semiconductor interposing shield.